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Top Stories — June 18, 2014
3D memory for future nanoelectronic systems
Bit-growth slows while specialized stacking accelerates innovation in future memory solutions for communications, energy, and health-care.
New materials and processes for advanced interconnects
Although on-chip interconnects have not been scaling at the same speed as other parts of the chip, new capabilities enabled by graphene and CNTs, among other materials, could soon change that.
Qualcomm: Scaling down is not cost-economic anymore - so we are looking at true monolithic 3D
Over the course of three major industry conferences (VLSI 2013, IEDM 2013 and DAC 2014), executives of Qualcomm voiced a call for monolithic 3D "to extend the semiconductor roadmap way beyond the 2D scaling" as part of their keynote presentations.
In-line high-K/metal gate monitoring using picosecond ultrasonics
Only a direct measurement of SRAM structures can represent true variations of metal gate height due to CMP process and is strongly affected by the design and layout of pattern, including pattern density, dummy design, and spacing.
Towards all solid-state 3D thin-film batteries for durable and fast storage
One way to make Li-ion batteries more durable, safer, smaller and in particularly faster, is a transition towards all solid-state 3D thin-film Li-ion batteries.
Down to 5nm: Scaling with the usual suspects – performance, cost
While there may be a non-EUV roadmap to 7nm, what will happen by 5nm is not so clear since by the time we get there silicon may have run out of steam.
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News & Features
Research Alert: June 17, 2014
Research on high-performance field-effect transistors; UC Santa Barbara researchers introduce highest performing III-V metal-oxide semiconductor FET
Blog review June 16, 2014
New blogs give a preview of an upcoming MEMS webcast; look at the Synopsys Galaxy Design platform's support of FD-SOI; presentations from the recent Symposium on Polymers; SEMI's role in supporting legislation in the U.S., Qualcomm's call for monolithic 3D; and why some companies still struggle with predicting financial operational performance.
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Blogs/Twitter
Applied Innovation
New Materials Era in Advanced Interconnects
Today's announcement of the Applied Endura?® Volta™ CVD Cobalt system, which deposits thin conformal and selective cobalt films ...
ASN's All Things SOI
Synopsys Design Flow Support for Samsung-ST 28nm FD-SOI
The Synopsys' Galaxy Design Platform has been extended to support the Samsung-STMicroelectronics strategic agreement on 28nm FD-SOI.
Pete's Posts Blog
The Rise of MEMS Sensors
Join us for a MEMS-focused webcast on Thursday, June 19th at 12:00pm Eastern time. Presenters will be Jay ...
Insights From Leading Edge
IFTLE 196 2014 Symp on Polymers: Fraunhoffer IZM; ASE, Hitachi Chem
The 16th biennial Symposium on Polymers was held this May in Wilmington DE. Keynote speakers included Steve Bezuk, ...
Viewpoints: SEMI
SEMI Advocates for the Industry in Washington - Science, Innovation, R&D
With changes coming in Washington, SEMI has important work ahead supporting the innovators and job creators of this ...
EUVL Focus
Insertion of EUVL into fab: Challenges for 7nm insertion
While two chipmakers are reported to be working on inserting EUVL into fabs for manufacturing at the 10nm ...
MEMS Industry Group Blog
Thoughts on MIG Conference Japan
I am finally over the jet lag and able to share my thoughts from MEMS Industry Group (MIG) ...
IC Design
Full Reliability Automation Is Here!
Transistor and Gate levels of library design are normally delivered fully vetted for reliability issues such as electrostatic ...
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Videos/Podcasts
Solid State Watch: June 6-12, 2014
Entropic consolidation; Field-effect transistor research, 2014 Symposium on VLSI Technology; ON Semiconductor to acquire Aptina Imaging
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White Papers
RF-SOI Wafers for Wireless Applications
The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
DFM: What is it and what will it do?
Everybody's talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
Via Doubling to Improve Yield
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
The Impact Of 14-nm Photomask Uncertainties on Computational Lithography Solutions
Certain measurement methodologies can be inaccurate even if they're precise, and there are known errors associated with certain system parameters.
A Study Of Model-Based Etch Bias Retarget For OPC
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
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