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Top Stories — May 21, 2014
ST licenses 28nm FD-SOI to Samsung
Samsung joins GLOBALFOUNDRIES in offering performance boost in 2D silicon.
Scouting report for materials at end of the road: 2013 ITRS
When pavement ends the terrain gets rough, as documented in Emerging Research Materials chapter of newest ITRS.
Wafer-level packaging of ICs for mobile systems of the future
The most functionality at the least cost is the promise of wafer-level packaging (WLP) when dealing with complex integrated circuits (IC) with a high number of input/output connections to the outside world.
New materials and processes for advanced interconnects
Although on-chip interconnects have not been scaling at the same speed as other parts of the chip, new capabilities enabled by graphene and CNTs, among other materials, could soon change that.
GLOBALFOUNDRIES and Samsung join forces on 14nm finFETs
GLOBALFOUNDRIES and Samsung are announcing a joint program for 14nm FinFETs that offers a single process design kit (PDK) and manufacturing at four different fabs with identical processes.
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News & Features
Research Alert: May 20, 2014
Lighting the way to graphene-based devices; SMIC and other groups collaborate to setup the "IC Advanced Technology Research Institute"; What to look for at IITC
Blog review May 5, 2014
New blogs look at how the Internet of Things (IoT) will mostly use devices that can be produced by legacy fabs, the value of body biasing and SOI, reliability concerns that designers need to address, and the newly released International Technology Roadmap for Semiconductors (ITRS).
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Pete's Posts Blog
GLOBALFOUNDRIES' Kengeri to speak at The ConFab
Subramani Kengeri, Vice President, Advanced Technology Architecture at GLOBALFOUNDRIES will speak at The ConFab 2014 on the "techno-economics" ...
Applied Innovation
Can Legacy Fabs Keep Up With IoT Demand?
The Internet of Things (IoT) is set to drive demand and innovation in the semiconductor market over the ...
ASN's All Things SOI
Body Biasing in FD-SOI: A Designer's Nightmare Or A Longtime Friend?
One of the unique features of the FD-SOI technology is the ability of using a wide range of ...
Insights From Leading Edge
IFTLE 193 SEMI Singapore Part 2: SPTS and STATSChipPAC
At the recent 2.5/3DIC Forum at SEMI Singapore Dr. Surya Bhattacharya, Director of Industry Development (TSV) at, A*STAR ...
IC Design
Full Reliability Automation Is Here!
Transistor and Gate levels of library design are normally delivered fully vetted for reliability issues such as electrostatic ...
EUVL Focus
Insertion of EUVL into fab: Challenges for 7nm insertion
While two chipmakers are reported to be working on inserting EUVL into fabs for manufacturing at the 10nm ...
MEMS Industry Group Blog
Thoughts on MIG Conference Japan
I am finally over the jet lag and able to share my thoughts from MEMS Industry Group (MIG) ...
Viewpoints: SEMI
The Sustainable Manufacturing Imperative
Companies in the microelectronics manufacturing supply loop see "sustainability" as an important objective in their operations as well...
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Solid State Watch: May 9-15, 2014
STMicroelectronics licenses 28nm FD-SOI to Samsung; DoD policy to reduce counterfeit semiconductors; OLED market growth; Applied Materials releases new CVD system
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White Papers
RF-SOI Wafers for Wireless Applications
The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
DFM: What is it and what will it do?
Everybody's talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
Via Doubling to Improve Yield
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
The Impact Of 14-nm Photomask Uncertainties on Computational Lithography Solutions
Certain measurement methodologies can be inaccurate even if they're precise, and there are known errors associated with certain system parameters.
A Study Of Model-Based Etch Bias Retarget For OPC
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
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