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Top Stories — April 17, 2014
GLOBALFOUNDRIES and Samsung join forces on 14nm finFETs
Fabless companies could skip the 20nm node and move straight to 14nm FinFETs. That is the hope of GLOBALFOUNDRIES and Samsung who are announcing a joint program that offers a single process design kit (PDK) and manufacturing at four different fabs with identical processes. The PDKs are available now, and 14nm manufacturing could move into high volume production by the end of the year.
IP interoperability in SoCs: Mix and match doesn't always work
More often than not, a design re-spin isn't just a simple re-spin with a tweak here and a tweak there. The new design will probably have to comply with modified specifications that inevitably raise the bar for performance and power usage, and it will probably contain new IP that must be integrated.
Going Up! Monolithic 3D As An Alternative to CMOS Scaling
At CEA-Leti in Grenoble (France), one of the world's most advanced microelectronics R&D centers, CMOS-device teams are exploring various routes to meet increased performance requirements of future semiconductor applications. M3D is a primary focus in the search for alternate routes to scaling, in addition to other disruptive approaches such as steep slope devices, mechanical switches based on NEMS and single electron transistors.
3D EDA brings together proven 2D solutions
With anticipated economic limits to the continuation of Moore's Law now on the horizon, it seems that moving into the 3rd dimension (3D) by stacking multiple layers of integrated circuits (IC) will be the ultimate expression of CMOS technology. Whether stacking heterogeneous chips using through-silicon vias (TSV), or monolithic approaches to forming multiple active IC layers on a single silicon substrate, 3D ICs should be both smaller and faster compared to functionally equivalent 2D chips and packages.
Roll over flat panel displays
Flexible displays is a technological field that has been in R&D and pre-commercial development for several years, but what needs to happen to make volume production a reality, in areas including substrates, materials and production processes? Semiconductor Manufacturing & Design discussed the issues with Mac McDaniel, Director and Chief Marketing Officer, Display Business Group, Applied Materials, Michael Ciesinski, MD of the Flextech Alliance, and Keri Goodwin, Principal Scientist from the Centre for Process Innovation (CPI), in the UK.
Solid State Technology March 2014
The latest issue of Solid State Technology reports on ways to reduce polymer defects in metal etch, advantages of SiC for power devices, how to improve efficiency in semiconductor R&D, an IBM report on SOI, and a report on Ag plating in HBLED packaging.
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News & Features
Blog review April 14, 2014
New blogs provide a preview of The ConFab's keynote talk by Qualcomm's Roawen Chen, a review by CEA-Leti researchers on 3D integration with SOI, an analysis of the IMAPS Device Packaging Conference, and an overview of the issues surrounding sustainable manufacturing.
Catching the (invisible) wave
In a feat that may provide a promising array of applications, researchers at UC Santa Barbara have created a compound semiconductor of nearly perfect quality with embedded nanostructures containing ordered lines of atoms that can manipulate light energy in the mid-infrared range.
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Blogs/Twitter
Viewpoints: SEMI
The Sustainable Manufacturing Imperative
Companies in the microelectronics manufacturing supply loop see "sustainability" as an important objective in their operations as well ...
ASN's All Things SOI
Going Up! Monolithic 3D As An Alternative to CMOS Scaling
The miniaturization of the MOSFET transistor has been the main booster for the semiconductor industry's rapid growth in ...
Applied Innovation
CD-SEM Sees Beyond Less Than 10 Nanometer Nodes
At the recent SPIE Advanced Lithography conference, my keynote presentation focused on how improvements in metrology, multi-patterning techniques ...
Pete's Posts Blog
Extreme Stress for Existing Foundry/Fabless Model
The increased performance and the rapid shift from traditional handsets to consumer computing device post a number of ...
Insights From Leading Edge
IFTLE 188 IMAPS Device Packaging Conf Part 2: AMD, SCP
Continuing our look at the recent IMAPS DPC with several key presentations.
MEMS Industry Group Blog
MEMS - Enter with Care
MEMS - enter with care. I think that will be my tagline for MEMS Industry Group's third annual ...
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Videos/Podcasts
Solid State Watch: April 4-10, 2014
February semi sales increase; Scalable CVD process for making 2-D molybdenum diselenide; MEMS microphone growth; SEMI releases report on semiconductor packaging materials
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White Papers
RF-SOI Wafers for Wireless Applications
The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
DFM: What is it and what will it do?
Everybody's talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
Via Doubling to Improve Yield
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
The Impact Of 14-nm Photomask Uncertainties on Computational Lithography Solutions
Certain measurement methodologies can be inaccurate even if they're precise, and there are known errors associated with certain system parameters.
A Study Of Model-Based Etch Bias Retarget For OPC
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
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