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Top Stories — March 26, 2014
3D EDA brings together proven 2D solutions
Design methodologies and technologies for 2D multi-chip systems are extended into 3D using proprietary tools based on industry standards.
Roll over flat panel displays
Flexible displays is a technological field that has been in R&D and pre-commercial development for several years, but what needs to happen to make volume production a reality, in areas including substrates, materials and production processes? Semiconductor Manufacturing & Design discussed the issues with Mac McDaniel, Director and Chief Marketing Officer, Display Business Group, Applied Materials, Michael Ciesinski, MD of the Flextech Alliance, and Keri Goodwin, Principal Scientist from the Centre for Process Innovation (CPI), in the UK.
Big sell: IP Trends and Strategies
Experts from Semico Research, Cadence, Uniquify and Sonics challenge growth trends for semiconductor intellectual property (SIP) with FinFETs, the IoT and more.
IP interoperability in SoCs: Mix and match doesn"t always work
More often than not, a design re-spin isn"t just a simple re-spin with a tweak here and a tweak there. The new design will probably have to comply with modified specifications that inevitably raise the bar for performance and power usage, and it will probably contain new IP that must be integrated. At the same time, the design team will be told to leverage as much of the silicon-proven IP already in production as possible.
Solid State Technology March 2014
The latest issue of Solid State Technology reports on ways to reduce polymer defects in metal etch, advantages of SiC for power devices, how to improve efficiency in semiconductor R&D, an IBM report on SOI, and a report on Ag plating in HBLED packaging.
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News & Features
Research Alert: March 18, 2014
Creating a graphene-metal sandwich to improve electronics; Surface characteristics influence cellular growth on semiconductor material; First methodology to analyze nanometer line pattern images
Blog review March 24, 2014
New blogs take a look at a new IBS analysis of FDSOI, an upcoming webcast on 3D Integration and lithography, and a long angry speech of scorn and criticism on packaging nomenclature, condensed and articulated.
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Applied Innovation
Enabling Wearable Electronics in the Internet of Things (IoT) Era
As part of its growth focus for Applied Materials, the Office of the CTO (Chief Technology Officer) aims ...
ASN's All Things SOI
Why Migration to FD-SOI Is A Better Approach than Bulk CMOS and FinFETs at 20nm and 14/16nm For Price-Sensitive Markets
IBS has recently issued a new white paper entitled Why Migration to 20nm Bulk CMOS and 16/14nm FinFETs ...
IC Design
If you fear change, ECO fill can help
You know the feeling. You walk out of the grocery store with a cart full of bags, and ...
Pete's Posts Blog
Webcast on 3D Integration/Advanced Packaging, Lithography
If you've been following the field of 3D integration for any time at all, then you're familiar with ...
Insights From Leading Edge
IFTLE 185 Lecturing the Packaging Community on Nomenclature
The word "lecture" is one of those wonderful English words with multiple meanings. Lecture can mean "a talk ...
Intel's e-DRAM Shows Up In The Wild
When Intel launched their Haswell series chips last June, they stated that the high-end systems would have embedded ...
Semico Spotlight
SIA's January Release Corroborates Semico's IPI Prediction
On March 2, 2014 SIA announced that worldwide sales of semiconductors reached $26.3 billion for the month of ...
EUVL Focus
State of EUVL - Challenges of HVM Introduction
Most of the papers at this year's EUVL Conference during SPIE's 2014 Advanced Lithography program focused on ...
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Solid State Watch: March 14-20, 2014
Toshiba and SanDisk sue SK Hynix; Berkeley research on on-chip inductors; EV Group opens HQ in China; SEMI awards SMIC CEO with Outstanding EHS Achievement Award
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White Papers
RF-SOI Wafers for Wireless Applications
The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
DFM: What is it and what will it do?
Everybody's talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
Via Doubling to Improve Yield
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
The Impact Of 14-nm Photomask Uncertainties on Computational Lithography Solutions
Certain measurement methodologies can be inaccurate even if they're precise, and there are known errors associated with certain system parameters.
A Study Of Model-Based Etch Bias Retarget For OPC
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
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Semiconductor Manufacturing & Design Newsletter is published monthly and contains deep insights for chip architects and engineers. SemiMD is published by Extension Media LLC and is part of the Chip Design Network.
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