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Top Stories — December 17, 2013
FinFET on SOI: Potential Becomes Reality
By using SOI-based FinFET technology, the need for doping in the body has been effectively minimized, resulting in excellent matching characteristics in the undoped DRAM transfer device, and truly remarkable minimum operating voltage in the SRAM.
Experts Roundtable: Exploring the relationship between board-level design and 3D, and stacked dies
SemiMD discussed what board level design can tell us about chip-level (three-dimensional) 3D and stacked dies with Sesh Ramaswami of Applied Materials and Kevin Rinebold of Cadence.
GLOBALFOUNDRIES, Open-Silicon and Amkor demo 2.5D test vehicle
GLOBALFOUNDRIES, Open-Silicon and Amkor Technology have jointly exhibited a functional system-on-chip (SoC) solution on a 2.5D silicon interposer featuring two 28nm logic chips, with embedded ARM processors.
Advances in Post-Tape Out Resource Management
Foundries, both pure-play and independent device manufacturers (IDM), rigorously compete for market share. One factor that helps them get and keep business is turnaround time (TAT). As technology nodes advance, achieving targeted production runtimes in the post-tapeout flow gets ever more challenging.
Eliminating the Challenges of Giga-Scale Circuit Design with Nano-Scale Technologies
Dr. Lianfeng Yang of ProPlus Design Solutions, Inc. says that the only way out of today's challenges is to more tightly integrate tools for nano-scale modeling, giga-scale SPICE simulation and DFY.
Slideshow: 2013 IEDM Highlights
Highlights from this year's International Electron Devices Meeting (IEDM) include breakthroughs in silicon and non-silicon device technology, molecular electronics, nanotechnology, optoelectronics, MEM/NEMS, energy-related devices and bioelectronics.
AMD and Hynix announce joint development of HBM memory stacks
3DIC memory, and therefore all of 2.5/3D technology, took one step closer to full commercialization last week with the HBM joint development announcement from AMD and Hynix at the RTI 3D ASIP meeting in Burlingame CA.
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News & Features
Research Alert: Dec. 10, 2013
Thin, flexible solar cells; Polymers can be semimetals; MOF materials
Blog review December 16, 2013
New blogs celebrate the 66th anniversary of the transistor, a joint development announcement from AMD and Hynix focused on high bandwidth memory, 20 years of BSIM SPICE models, more details on the merger between Applied Materials and TEL, and a report on IEDM.
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Applied Innovation
Happy 66th, Transistor!
Today marks the 66th birthday of the first working transistor; an opportune time to look back at how ...
ASN's All Things SOI
ASN Exclusive Interview: Skyworks on SOI for RF
Skyworks has a growing portfolio of chips on SOI. Kevin Walsh, the company's Marketing Director of Analog Solutions, ...
Pete's Posts Blog
Challenges of 10nm and 7nm CMOS at IEDM
Process technology (including litho) and process integration remains the most critical factor in determining success moving forward. ...
Insights From Leading Edge
IFTLE 172 Sony TSV Stacked CMOS Image Sensors Finally Arrive in 2013
Many of us can recall 2008 when Toshiba commercialized the first CMOS image sensor with TSV last /backside. ...
IEDM 2013 Preview
Next week, the researchers and practitioners of the electron device world will be gathering in Washington D.C. for ...
MEMS Industry Group Blog
MEMS: An Enabler of the Next Internet Revolution
Micro-electromechanical systems (MEMS) and sensor fusion will play a critical role in enabling a more intelligent and intuitive ...
Semico Spotlight
What I Learned on the Way to the Semico Impact Conference: Focus on the IP Ecosystem
I had a very interesting discussion with Sundar Iyer, CEO of Memoir Systems, during a briefing they gave ...
EUVL Focus
Source Workshop Presents Data on Readiness of 50 W EUV Sources to Support EUVL Scanners
The 2013 Source Workshop (Nov 3-7, 2013, Dublin, Ireland) brought together one of the world's largest annual gatherings ...
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Solid State Watch: September 20-26
Applied Materials to merge with Tokyo Electron; Micron ships first samples of HMC; RFMD introduces 6-inch GaN-on-SiC wafers; Semi manufacturing equipment spending down
From SEMICON West 2013: Stephen Pateras of Mentor Graphics
John Blyler interview Stephen Pateras, Product Marketing Manager of Mentor Graphics
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White Papers
RF-SOI Wafers for Wireless Applications
The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
DFM: What is it and what will it do?
Everybody's talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
Via Doubling to Improve Yield
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
The Impact Of 14-nm Photomask Uncertainties on Computational Lithography Solutions
Certain measurement methodologies can be inaccurate even if they're precise, and there are known errors associated with certain system parameters.
A Study Of Model-Based Etch Bias Retarget For OPC
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
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Semiconductor Manufacturing & Design Newsletter is published monthly and contains deep insights for chip architects and engineers. SemiMD is published by Extension Media LLC and is part of the Solid State Technology Network.
Editor in Chief: John Blyler