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Top Stories
— November 13, 2013
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Progress on 450mm at G450C
Paul Farrar, general manager of G450C, said 25 tools will be installed in the Albany cleanroom by the end of 2013, progress has been made on notchless wafers and wafer quality, and automation and wafer carriers are working well.
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Experts Roundtable: DFY moves closer to the foundry/manufacturing side
SemiMD discussed the trend for design for yield moving closer to the foundry/manufacturing side with experts from ProPlus Design Solutions, Cadence, Mentor Graphics and Applied Materials.
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Model-based hints: GPS for LFD success
Layout modifications needed to fix litho hotspots must be made by the designer, who is generally not familiar with post-tapeout processes, EDA tools need to provide the designer with some help during this fix process.
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Packaging materials trends: Mobility is the key market driver
Advancements in materials technology and new materials will be needed to solve challenges pertaining to device and system integration and to package and system reliability. Semiconductor manufacturers and packaging subcontractors have identified a number of concerns, unmet material needs, and opportunities for material suppliers.
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Design for Yield trends
Should foundries establish and share best practices to manage sub-nanometer effects to improve yield and also manufacturability?
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Monte Carlo Analysis has become a gamble
Dr. Bruce McGaughy, CTO and SVP of Engineering at ProPlus Design Solutions, Inc. discusses the wisdom of Monte Carlo analysis when high sigma methods are perhaps better suited to today’s designs.
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Managing legacy fabs and the role of secondary equipment
The choice between buying new systems from OEMs or fully capable refurbished gear from qualified used equipment vendors is examined.
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more top stories 
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News & Features
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Research News: Nov. 12, 2013
Synaptic transistor learns while it computes; Diamond imperfections pave the way to technology gold; The next big thing in the energy sector: Photovoltaic generated DC energy
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Blog Review November 11, 2013
New blogs delve into the impact of pervasive computing on the semiconductor industry, the opportunities in MEMS, flipchip market research, bump-on-polymer reliability, chip embedding, lifetime concerns of EUV optics, a curious take on Moore's Law and SST's new editorial calendar for 2014.
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Our Sponsors
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Videos/Podcasts
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| Solid State Watch: Nov. 1-7, 2013 |
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| imec demonstrates III-V finFETs; Rubicon launches large diameter sapphire substrates; the flexible display market growth; SRC's RF research |
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| SRC TECHCON 2013: Nanometer IC Design for Manufacturability |
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| Winner of the 2013 Technical Excellence Award, Professor David Pan of University of Texas/Austin, discusses his research. |
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More Videos/Podcasts
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White Papers
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| DFM: What is it and what will it do? |
| Everybody's talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda. |
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| Via Doubling to Improve Yield |
| In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area. |
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