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Top Stories — October 24, 2013
Applied Materials rolls out new CVD and PVD systems for IGZO-based displays
Applied Materials introduced three new tools for the display market aimed at metal oxide thin film transistors.
Marrying diversification, innovation with high-volume manufacturing – the MEMS puzzle
The explosive growth of the iPhone motion sensing smart phone market has pushed the MEMS industry into high-volume demand. Can they meet demand?
Defect-Free Mask Blanks Next EUV Challenge
The next major roadblock to progress in the ongoing push to develop EUV lithography for volume production is the availability of defect-free mask blanks.
Experts Roundtable: More than Moore – manufacturing challenges for MEMS
Semiconductor Design & Manufacturing discussed ‘More than Moore‘ (MtM) standardization topics and challenges with Peter Himes, VP of marketing and strategic alliances at Silex Microsystems, Dr Eric Mounier, senior analyst, MEMS devices and technologies at Yole Développement, Tom Morrow, chief marketing officer at SEMI and Mike Rosa, senior global product strategic marketing manager – emerging technologies, 200mm components and systems group at Applied Materials. What follows are excerpts of that conversation.
Scaling Makes Monolithic 3D Practical
In the 1960s, James Early of Bell Labs proposed three-dimensional structures as a natural evolution for integrated circuits. Since then many attempts have been made to develop such a technology.
Inside the Hybrid Memory Cube
The HMC provides a breakthrough solution that delivers unmatched performance with the utmost reliability.
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News & Features
Research Bits: Oct. 22, 2013
Size matters in the giant magnetoresistance effect in semiconductors; Thin film semiconductors that will drive production of next-generation displays; Ultraviolet light to the extreme
Blog Review October 21 2013
EUV on time for 10nm, mask defectivity an issue, pellicles an option, source power timing; DSA very promising; Intel delays 14nm production; FinFETS tech of choice; Intel stands firm on 450mm; Market reports from Semicon Taiwan.
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Blogs/Twitter
Applied Innovation
Materials Innovation Key To Enabling Next-Generation Mobile Devices
The next cool gadgets will require new materials, new technology nodes and new architectures.
IC Packaging
Take Notes During Your Packaging Design Workflow with the Database Diary
In this blog, we take a look, not at a new command, but instead at a classic command ...
Semico Spotlight
IP Subsystems: Is It A Catalyst for Leading Edge Design Enablement
The System-on-Chip (SoC) market has been successful because of the increasing use of 3rd Party Semiconductor Intellectual Property ...
ASN's All Things SOI
Peregrine BSOS RF Chip in Samsung Galaxy S4 LTE-A - That's SOI!
Main antenna switch solves complex carrier aggregation; simultaneous operation of up to 14 bands
The Foundry Files
MEMS Explosion
The latest milestones and future trends for making MEMS a mainstream technology.
EUVL Focus
Advancing EUV Source Technology - 2013 Source Workshop (November 3-7, 2013, Dublin, Ireland)
Pete's Posts Blog
EUV is late but on the way for 10nm; DSA is promising
Insights From Leading Edge
IFTLE 165 Semicon Taiwan contd: DRAM Consolidation, Smartphone Mkt; Packaging Materials Forecast
Viewpoints: SEMI
Japan: Latest Investment Activities
Higher spending for memory and power semiconductors will drive double-digit growth.
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Videos/Podcasts
From SEMICON West 2013: Paul Boudre of Soitec
Soitec's COO Paul Boudre talks about the competitiveness of full-depleted planar with full-depleted finfet; capacity issues for SOI in light of ST's open foundry model; and growth of High Resistivity SOI in the RF implementation on smart phones.
From SRC TECHCON 2013: Cross-Layer Research in Microarchitecture and Physics
Researchers discuss their projects at SRC TECHCON 2013. William Song, Georgia Institute of Technology
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White Papers
DFM: What is it and what will it do?
Everybody's talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
Via Doubling to Improve Yield
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
The Impact Of 14-nm Photomask Uncertainties on Computational Lithography Solutions
Certain measurement methodologies can be inaccurate even if they're precise, and there are known errors associated with certain system parameters.
A Study Of Model-Based Etch Bias Retarget For OPC
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
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