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IC Roadmap Remains in Flux Amid Scaling Challenges |
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The technology roadmap for semiconductors remains in flux, as there are more signs that the foundries may accelerate the insertion point for finFETs. And adding more uncertainty to the IC roadmap, various factions at a recent event debated over which technology – bulk, SOI or SuVolta – will scale and enable future designs. |
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GlobalFoundries Enters 2.5D/3D Chip Foundry Market |
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Setting the stage for intense competition in an emerging market, GlobalFoundries has officially entered the 2.5D/3D chip-stacking foundry arena. The company's 2.5D/3D foundry strategy is far different than that of one major rival: Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC). |
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Industry Inches Towards Standard PDK for Foundries |
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For years, the analog and mixed-signal industry has been talking about the need for a standard and interoperable process design kit (PDK) to reduce costs and speed up the design cycles in a foundry. But to date, the advent of a single and standard PDK remains elusive, as various factions still agree to disagree about the future of the technology. |
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Semiconductor Manufacturing Research News |
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Silicon nanodots could store charge in a form of non-volatile memory being studied at Berkeley and elsewhere. Illinois researchers are learning how a single atomic layer can disrupt or enhance heat flow across an interface, knowledge which may prove useful in ICs and thermoelectric devices. |
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KLA-Tencor Introduces Clustered Inspection Tool |
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KLA-Tencor put a clustered wafer defect inspection/metrology/review system on the market. The CIRCL tool "does with parallel processing what had previously been running serially," a marketing manager said, including front side, back side, and wafer edge inspection. |
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Adaptive Test Set To Go Mainstream in ATE World |
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Seeking to drive down IC test costs, the industry is looking at new methods and standards for a promising technology called adaptive test. This technology has been used by select IC makers. More recently, a new crop of third-party adaptive software suppliers have emerged in the market. |
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Soitec Touts FD-2D and FD-3D on SOI Wafers |
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Soitec is rolling out its SOI solution for fully-depleted CMOS, saying it can support planar (FD-2D) and vertical (FD-3D) technologies. By using the SOI wafer's buried oxide layer intelligently, the number of process steps can be sharply reduced, offsetting the cost of the SOI wafer, said Soitec's Steve Longoria. |
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FinFETs, HKMG on 2012 VLSI Symposium Program |
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Intel will detail its 22nm tri-gate technology and related MPU work at the VLSI symposia in June. FinFETs and nanowire-related work will lead off the Symposium on VLSI Technology, set for Honolulu. IBM and its R&D partners will describe their planar and finFET transistor research, along with a paper on the alliance's gate-last HKMG approach. |
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New DFM and Verification Hurdles Seen at 20/14nm |
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For years, the shift to the next process node has always presented new, difficult and sometimes costly challenges in the IC manufacturing flow. From a DFM and physical verification standpoint, chip makers will face some new challenges at 20nm and 14nm. So what's coming down the pike in this arena? |
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Wanted: New Memory Type for Supercomputing |
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The shift towards a new class of exascale computers will require new breakthroughs in power management and chip-level technologies like memories, according to a technologist. Targeted by 2018 or so, exascale systems are supercomputers that be used for climate modeling, defense, Internet searching, medicine, physics and other applications. |
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