Semiconductor Manufacturing & Design Community Subscribe
IN THIS ISSUE — April 30, 2012
1. News & Features
2. Blogs
IC Roadmap Remains in Flux Amid Scaling Challenges
The technology roadmap for semiconductors remains in flux, as there are more signs that the foundries may accelerate the insertion point for finFETs. And adding more uncertainty to the IC roadmap, various factions at a recent event debated over which technology – bulk, SOI or SuVolta – will scale and enable future designs.
GlobalFoundries Enters 2.5D/3D Chip Foundry Market
Setting the stage for intense competition in an emerging market, GlobalFoundries has officially entered the 2.5D/3D chip-stacking foundry arena. The company's 2.5D/3D foundry strategy is far different than that of one major rival: Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC).
Industry Inches Towards Standard PDK for Foundries
For years, the analog and mixed-signal industry has been talking about the need for a standard and interoperable process design kit (PDK) to reduce costs and speed up the design cycles in a foundry. But to date, the advent of a single and standard PDK remains elusive, as various factions still agree to disagree about the future of the technology.
Semiconductor Manufacturing Research News
Silicon nanodots could store charge in a form of non-volatile memory being studied at Berkeley and elsewhere. Illinois researchers are learning how a single atomic layer can disrupt or enhance heat flow across an interface, knowledge which may prove useful in ICs and thermoelectric devices.
KLA-Tencor Introduces Clustered Inspection Tool
KLA-Tencor put a clustered wafer defect inspection/metrology/review system on the market. The CIRCL tool "does with parallel processing what had previously been running serially," a marketing manager said, including front side, back side, and wafer edge inspection.
Adaptive Test Set To Go Mainstream in ATE World
Seeking to drive down IC test costs, the industry is looking at new methods and standards for a promising technology called adaptive test. This technology has been used by select IC makers. More recently, a new crop of third-party adaptive software suppliers have emerged in the market.
Soitec Touts FD-2D and FD-3D on SOI Wafers
Soitec is rolling out its SOI solution for fully-depleted CMOS, saying it can support planar (FD-2D) and vertical (FD-3D) technologies. By using the SOI wafer's buried oxide layer intelligently, the number of process steps can be sharply reduced, offsetting the cost of the SOI wafer, said Soitec's Steve Longoria.
FinFETs, HKMG on 2012 VLSI Symposium Program
Intel will detail its 22nm tri-gate technology and related MPU work at the VLSI symposia in June. FinFETs and nanowire-related work will lead off the Symposium on VLSI Technology, set for Honolulu. IBM and its R&D partners will describe their planar and finFET transistor research, along with a paper on the alliance's gate-last HKMG approach.
New DFM and Verification Hurdles Seen at 20/14nm
For years, the shift to the next process node has always presented new, difficult and sometimes costly challenges in the IC manufacturing flow. From a DFM and physical verification standpoint, chip makers will face some new challenges at 20nm and 14nm. So what's coming down the pike in this arena?
Wanted: New Memory Type for Supercomputing
The shift towards a new class of exascale computers will require new breakthroughs in power management and chip-level technologies like memories, according to a technologist. Targeted by 2018 or so, exascale systems are supercomputers that be used for climate modeling, defense, Internet searching, medicine, physics and other applications.
More News & Features
Editor's View

Chipworks Zooms In on Tri-gate
Chipworks technology analyst Dick James discusses the teardown company's images, and first conclusions, from the Intel 22nm tri-gate-based MPUs.
Semico Spin

Forecasting Wafer Demand: Technology Migration, Bottlenecks and Confetti
If you cover a long enough time period, the small ups and downs of a graphed line can look very smooth.
Mentor Musings

Three DFM "Litho" Checkpoints at SMIC
Design for manufacturing (DFM) has been an industry buzz word for several years, but now that it is an expected part of every design flow at 40nm and below, we are seeing how the concept of DFM can be successfully deployed.
Viewpoints: SEMI

2011: A Look Back at the Semiconductor Equipment and Materials Market and Outlook
2011 was a record year for the semiconductor industry in many regards. First and foremost, semiconductor revenues approached the long elusive $300 billion mark.
Litho Guru

If Computers Could Write
Would you buy a book written entirely by a computer? I did, and here is what I found.
ASN's All Things SOI

ST-Ericsson 28nm FD-SOI smartphone SOC, Q3 tape-out (interview)
Chief Chip Architect: less process complexity; solves scaling, leakage and variability issues

Incumbency rules ! – in lithography as elsewhere.
We were discussing the latest in lithography that were the subject of blogs by yours truly and Chris Mack. I was opining that there is a well establishes tradition in the industry that we whine about the cost and difficulty of each new technology, learn to live with it and then embrace it even if alternatives appear.
Riding the Silicon Rapids

EUV glass still less than half full, but level is rising
The rate of progress in EUV lithography is better than many perceive it to be.
Semi Mentor Applied Materials Soitec Global Foundries Novellus
Soitec COO Paul Boudre discusses what will be the best solution for 20nm – fully depleted silicon on insulator or bulk 3D transistors? The answer will likely include both.
Just how easy is to move designs from one foundry to another? It depends who you ask.
More Videos/Podcasts