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IN THIS ISSUE — September 01, 2011
1. News & Features
2. Round Table Discussions/Videos
3. Blogs
Older Nodes, Newer Process Technology
Rising costs at the leading edge of Moore’s Law are prompting investments at older nodes to retrofit processes for low power and higher performance. These changes are expected to be particularly significant in light of 3D stacking, which is expected to begin next year.
Planar versus FinFET Debate Continues at GTC 2011
GlobalFoundries technology executives said a planar transistor is the best solution for their leading-edge foundry customers at the 20nm node. Gregg Bartlett told reporters that Intel’s tri-gate technology may not support the multiple threshold voltages required by SoC designs.
Samsung, GlobalFoundries Cooperation Growing
GlobalFoundries and Samsung have jointly developed a low-power, high-performance process aimed at smartphones, tablets, and other mobile systems. The two foundries also are emphasizing an ability to second source each other at four different fabs. Samsung’s Ana Hunter said the LPH process offers "20 percent more performance at the same leakage" compared with the 28nm low-power process.
GlobalFoundries Tapes Out 20nm Test Chip
GlobalFoundries said it has taped out a 20nm test chip, using tools from the four leading EDA vendors. Mojy Chian, senior vice president of design enablement at GlobalFoundries, said customers "can begin targeting their designs" to the foundry’s 20nm technology.
Globalfoundries Confronts Issues and Plans Ahead
Challenges were faced at 32nm, but the company highlights successes with ecosystem IP, EDA and semiconductor partners while implementing on future nodes and technologies.
Applied Sees Softening Demand Across All Segments
Applied Materials executives said orders dropped by 25 percent in the company’s third fiscal quarter, ending July 31. "We plan to tighten discretionary spending while preserving our technology investments and customer-facing activities," said CFO George Davis.
KLA-Tencor Defect Review Tool ‘Ahead of Roadmap’
KLA-Tencor said its eDR-7000 wafer defect review system is capable of redetecting 10nm or smaller defects, at four times the throughput of its previous generation system. The tool features a faster stage, with less vibration, and an imaging system that provides a one micron field of view.
National Instruments Touts Test Capabilities
At NI Week, National Instruments emphasized new semiconductor and system evaluation and test solutions developed by Medtronic, Texas Instruments, Analog Devices, ST-Ericsson, and other customers. At the annual LabView user event, NI announced a much-faster Compact RIO board, based on an Intel quad-core processor.
More News & Features
SEMI Capex Forecast Complicated by "Pause"
The SEMI consensus forecast estimates equipment sales rising 12% to $44.3 billion in 2011, despite a brief period of capacity consolidation.
EUV Mask Defects: What Can We Do About Them?
Although mask makers have made masks for decades, reducing their defectivity remains a challenge. Why? The simple answer is their reflectivity and the process of making EUV mirrors.
Experts At The Table: Multi-Foundry Strategies
Last of three parts: The impact of 3D stacking and 3D structures; business changes and commoditization; competitive concerns; multisourcing at the leading edge.
More Round Table Discussions/Videos
Editor’s View

GTC 2011 Takeaways
GlobalFoundries will continue to add capacity, despite a market slowdown at trailing-edge technologies.

GlobalFoundries Expands Offerings With Partners
GlobalFoundries R&D with Samsung leads to 28nm fabs in the U.S., Korea, and Germany, and first tape-outs using leading EDA flows. Still with IBM, but also doing things with IMEC, Intermolecular, and PDF Solutions.
ASN’s All Things SOI

Does SOI matter to the designers using the chips?
An interview with Guenter Reiniger, Marketing Manager for NXP’s Automotive Sensors.

How to Print an electron
Printed electronics does not involve printing electrons, but you get the idea. Every start up and corporate research group have their own version of printed electronics using different semiconductors, dielectrics or metallization strategy. As usual, I like to focus on patterning.
Viewpoints: SEMI

Industry Leaders See a Promising but Challenging Future
Megatrends Pointing Upward — but Scaling, EUV, 450 Remain Major Hurdles
Semi Mentor Applied Materials Soitec Global Foundries Novellus
Just how easy is to move designs from one foundry to another? It depends who you ask.
What problems are we likely to face at future nodes and with 3D structures?
More Videos/Podcasts