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IN THIS ISSUE — September 01, 2011
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Older Nodes, Newer Process Technology |
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Rising costs at the leading edge of Moore’s Law are prompting investments at older nodes to retrofit processes for low power and higher performance. These changes are expected to be particularly significant in light of 3D stacking, which is expected to begin next year. |
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Planar versus FinFET Debate Continues at GTC 2011 |
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GlobalFoundries technology executives said a planar transistor is the best solution for their leading-edge foundry customers at the 20nm node. Gregg Bartlett told reporters that Intel’s tri-gate technology may not support the multiple threshold voltages required by SoC designs. |
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Samsung, GlobalFoundries Cooperation Growing |
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GlobalFoundries and Samsung have jointly developed a low-power, high-performance process aimed at smartphones, tablets, and other mobile systems. The two foundries also are emphasizing an ability to second source each other at four different fabs. Samsung’s Ana Hunter said the LPH process offers "20 percent more performance at the same leakage" compared with the 28nm low-power process. |
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GlobalFoundries Tapes Out 20nm Test Chip |
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GlobalFoundries said it has taped out a 20nm test chip, using tools from the four leading EDA vendors. Mojy Chian, senior vice president of design enablement at GlobalFoundries, said customers "can begin targeting their designs" to the foundry’s 20nm technology. |
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Globalfoundries Confronts Issues and Plans Ahead |
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Challenges were faced at 32nm, but the company highlights successes with ecosystem IP, EDA and semiconductor partners while implementing on future nodes and technologies. |
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Applied Sees Softening Demand Across All Segments |
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Applied Materials executives said orders dropped by 25 percent in the company’s third fiscal quarter, ending July 31. "We plan to tighten discretionary spending while preserving our technology investments and customer-facing activities," said CFO George Davis. |
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KLA-Tencor Defect Review Tool ‘Ahead of Roadmap’ |
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KLA-Tencor said its eDR-7000 wafer defect review system is capable of redetecting 10nm or smaller defects, at four times the throughput of its previous generation system. The tool features a faster stage, with less vibration, and an imaging system that provides a one micron field of view. |
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National Instruments Touts Test Capabilities |
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At NI Week, National Instruments emphasized new semiconductor and system evaluation and test solutions developed by Medtronic, Texas Instruments, Analog Devices, ST-Ericsson, and other customers. At the annual LabView user event, NI announced a much-faster Compact RIO board, based on an Intel quad-core processor. |
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More News & Features
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ROUND TABLE DISCUSSIONS / VIDEOS
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Editor’s View
GTC 2011 Takeaways
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GlobalFoundries will continue to add capacity, despite a market slowdown at trailing-edge technologies.
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Siliconisms
GlobalFoundries Expands Offerings With Partners
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GlobalFoundries R&D with Samsung leads to 28nm fabs in the U.S., Korea, and Germany, and first tape-outs using leading EDA flows. Still with IBM, but also doing things with IMEC, Intermolecular, and PDF Solutions.
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ImPatterning
How to Print an electron
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Printed electronics does not involve printing electrons, but you get the idea. Every start up and corporate research group have their own version of printed electronics using different semiconductors, dielectrics or metallization strategy. As usual, I like to focus on patterning.
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 | | | Just how easy is to move designs from one foundry to another? It depends who you ask. | |  | |
| | | What problems are we likely to face at future nodes and with 3D structures? | |
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More Videos/Podcasts
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