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First of three parts: The importance of through-silicon vias; the available of tools and standards; best guesses for how the technology will roll out.

TSMC chairman and CEO Morris Chang said the foundry will build a 450-mm wafer pilot line in the 2013-2014 time frame, and a volume 450-mm line by 2015-2016. However, analysts said the dual introduction of EUV and 450-mm wafers may cause scheduling conflicts.

The 450-mm wafer program at the International Sematech Manufacturing Initiative (ISMI) is moving from Austin to Albany, armed with $20 million in New York state funding to advance the program’s goals, said program manager Tom Jefferson.

Using an ARM Cortex processor as a prototyping vehicle, a group of companies within the SOI Consortium has used 20nm Ultra Thin Body SOI technology to gauge the power and performance of fully depleted UTB-SOI for mobile applications.

FinFET technology is “on a trajectory to go into mass production” at Intel and TSMC, says Berkeley professor Chenming Hu. But UTB-SOI has the advantage of being less complicated to develop. “I think UTB-SOI is going to have a future because it is a simpler technology than FinFETs” Hu said.

Using feedback mechanisms among a variety of EDA tool flows would allow designers to optimize incremental tapeouts to the benefit of the entire design-manufacturing ecosystem.

Air-gaps to lower dielectric constant of electrical insulating layers in 25nm MLC NAND Flash ICs designed by Micron and Intel, after Micron, Samsung, Toshiba used air-gaps accidentally.

Qualcomm CDMA Technologies said it will not use a high-k/metal gate (HKMG) process for most of the chips it makes at the 28nm node, sticking with a poly/SiON gate stack. The company described the rationale behind the strategy — which because of Qualcomm’s size will have a major impact on the foundry business — at the 2010 International Electron Devices Meeting (IEDM) held in San Francisco.

The technology competition to supply the source of EUV radiation for the next-generation lithography tools has long been divided between the laser-produced plasma (LPP) approach, favored by Cymer Inc. (San Diego) and Gigaphoton Inc. (Oyama, Japan), and the discharge-produced plasma (DPP) method supported by Xtreme Technologies GmbH (Aachen, Germany).

Semiconductor technologists face a crossroads at the 14nm node, when partially depleted, planar transistors are unlikely to deliver improvements in performance and power. Technologists at the recent International Electron Devices Meeting (IEDM) in San Francisco debated the relative merits of FinFETs (tall) versus extremely thin silicon on insulator, or ETSOI (thin).

The burgeoning market for chemicals and materials used in solar cells and modules is expected to grow to $16.9 billion in 2015, up from $6.5 billion in 2010, according to a jointly prepared report from SEMI and Linx-AEI Consulting…

SEMI’s Silicon Manufacturers Group (SMG) reported that worldwide silicon wafer area shipments increased by 40 percent in 2010 over the previous year. In its year-end analysis of the silicon wafer industry, SMG said revenues also improved by 45 percent last…

Veeco Instruments (Plainview, N.J.) is on track to become a billion-dollar company in 2011 as the company’s new “MaxBright” GaN MOCVD systems roll out to customers, Veeco CEO John Peeler said. Sales increased 38 percent in 2010 to $933 million ($300 million in Q4), of which about $800 million went to LED and solar customers.

This year’s Sematech Knowledge Series events include meetings on lithography, wafer cleaning, gate stacks, and manufacturing productivity, among a variety of topics aimed at exploring critical technology challenges and building industry consensus.

Rudolph Technologies, Inc. (Flanders, N.J.) CEO Paul McLaughlin said the company’s inspection tools for advanced packages used in smart phones helped drive strong growth in 2010. And he said Rudolph’s inspection and metrology sales picture for 2011 is brightened by…

Just how real is 3D stacking and what are the main hurdles that need to be solved?

Via fanout and trace routing solutions for metric pitch ball grid array packages.

Xavier Cauchy, digital applications manager at Soitec, describes the design implications of fully depleted SOI technology at the 22/20 nm node.

Xavier Cauchy of Soitec and François Andrieu at LETI raise some of the technical issues surrounding fully depleted SOI technology. The authors compare FD-SOI to FinFETs, describe how non-digital transistors can be handled, and provide a list of references for further reading.

This Mentor Graphics paper describes the physical signoff challenges seen in advanced node designs.