New blogs examine the future of NAND flash memory, a preview of the International Electron Devices Meeting (IEDM) – is it time to think about the end of silcon? – Skyworks’ use of SOI, the Sony ISX014 8MP sensor, MEMS and the Internet of Things, and The ConFab, which will be held June 22-25, 2014 in Las Vegas.
New blogs discuss the best way to verify multi-IP, multiple power domain SoCs, contemplate what TSMC may have changed in 20nm devices from the 28nm generation, what happens when we run out of room “at the bottom” around 4nm, the recent EUV lithography workshop, presentations from The ConFab last month, and Qualcomm’s perspective on 3D integration.
New blogs give several different perspectives on Moore’s Law and the potential for continued scaling, the persistent uncertainty of EUV lithography, the VLSI Symposia and FD-SOI, and the recent Suss Technology Forum.
New blogs address the Internet of Things, which TSMC’s John Lin sees as the next big thing after mobile devices; Applied Materials’ new Volta system design around cobalt liners and capping layers; Soitec’s Christophe Maleville’s view on FDSOI; the recent SEMI 2.5/3D IC forum in Singapore; questions surrounding EUV lithography’s insertion into volume manufacturing, and the MEMS Industry Group’s Conference in Japan.
New blogs discuss metrology in the age of 3D memory, the many benefits of FDSOI, this year’s IMAPS Device Packaging Conference, the recent MEMS Industry Group meeting in Europe, and the upcoming R&D panel session at The ConFab in June.
More often than not, a design re-spin isn’t just a simple re-spin with a tweak here and a tweak there. The new design will probably have to comply with modified specifications that inevitably raise the bar for performance and power usage, and it will probably contain new IP that must be integrated.
Design methodologies and technologies for 2D multi-chip systems are extended into 3D using proprietary tools based on industry standards.
New blogs take a look The ConFab, where Dr. Gary Patton of IBM will provide a keynote talk, Applied Materials’ success working with Lawrence Berkeley Lab, ST’s view of FDSOI, the recent RTI- Architectures for Semiconductor & Packaging conference, the EUVL Conference during SPIE’s advanced litho program, and the newly-reported numbers for January: the best ever!
New blogs take a look at design challenges associated with re-filling an engineering change orders (ECOs), this year’s ISS meeting, and the pervasiveness of cheap silicon.
New blogs take a look at recent reports from G450C showing good results for major process steps and inspection (although cost benefits remain to be proven), new FD-SOI results demonstrating a 10X faster DSP, the need for high sigma yield brought on by the move to 28/20nm and 16nm, Obama’s policy impact on the semiconductor industry, the recent IEEE 3D IC and GaTech Interposer meetings, and the latest nanotechnology-use survey from NCMS.
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The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.
EUV will introduce unwanted patterning distortions that must be accurately modeled and corrected.
How to tame data file sizes, address fractured data files creation and streamline data review techniques.