Incumbency rules! – in lithography as elsewhere.
by Michael P.C. Watts
If double patterning gets established is it just a stop gap until EUV ? This was the entertaining subject at coffee with my editor at semimd (the great thing about writing a free blog is that you get to buy your own coffee when you meet – and yes, we need to find something more fun to talk about !)
We were discussing the latest in lithography that were the subject of blogs by yours truly and Chris Mack. I was opining that there is a well establishes tradition in the industry that we whine about the cost and difficulty of each new technology, learn to live with it and then embrace it even if alternatives appear. It seems inevitable that the industry will embrace double patterning for at least one node. I suspect that once the psychological barrier of double patterning has been overcome, defect densities will been driven down, we will learn to live with the challenges, and the reality of scaling will sink in. Double patterning will roughly double the cost of lithography, but will enable 4 x in transistor count. There will still be a cost advantage to shrinking, just not as much of an advantage as in the past. This same scaling will apply to triple and quad patterning.
Industry traditionally has always favored incumbency over new risks- just look at the history of optical lithography whose demise has been predicated for 30 years. I suspect that once double patterning is accepted it will be very difficult for any alternative with any new risks to break in.
About the Author
Mike Watts has been patterning since 1 um was the critical barrier, in other words for a longtime. I am a tall limey who is failing to develop a Texas accent here in Austin. I have a consulting shingle at www.impattern.com.
My blog “ImPattering” will focus on the latest developments in the business and technology of patterning. I am particularly interested in trying to identify how the latest commercial applications evolve.
April 16th, 2012 at 6:08 am
For a 4x transistor density improvement I can only think that might occur in cross-grid memory structures where say bit lines are defined in one mask and orthogonal word lines in another. However you will still have challenges with fan-out in row and column decoders. The design compliance restrictions in going to 2x shrink in one direction are pretty onerous. In practice just getting a single node shrink i.e. doubling of transistors by going to double patterning means you are doing pretty well. See the paper: “Double Patterning addressing Imaging challenges for near and sub k1=0.25 node layouts.” Photomask Japan 2009 73791N. Meanwhile due to 3-way symmetries DRAMs cannot benefit from double patterning at all.
February 11th, 2013 at 11:17 pm
Very good write-up. I absolutely appreciate this website.
Continue the good work!