Advanced Semiconductor Device Lithography – pushing the optical limit for lithography
Michael P. C. Watts
Given that the alternatives all have challenges, it looks to me that optical lithography will have to deliver the 16 nm and most likely the 11 nm node. In my last blog, I reviewed the news from SPIE’s Advanced Lithography conference on all the non-optical solutions. My conclusion was that in the best case, EUV and imprint could just make the 11 nm node but both have outstanding issues, the earliest e-beam could make is the 4 nm node.
In this blog I will consider the multiple paths to extend optical, which I will “simplify” down to; low k imaging, random interleaved double pattern, X&Y axis double pattern, sidewall frequency doubling, and directed self-assembly frequency multiplication. Most of these options have the word “doubling” in them, so the solution for 22 nm will be doubled and extend to the 11 nm node, so I will focus on the solutions for 11 nm node.
Let’s start at the simplest, low k imaging or simply printing with lower contrast images. The logic guys print their irregular features at a resolution of 0.5 x wavelength/Numerical Aperture, and the memory guys print regular features at 0.25 x wavelength/Numerical Aperture, “k” of 0.5 and 0.25 respectively. This is so close to the resolution limit that the image is a low contrast sine wave. In order to obtain the desired features with sufficient process window, all sorts of heroics such as custom illumination and correction for subsequent thermal distortions, and unique mask features are needed. These were discussed at length at the conference and associated commercial mini-conferences such as Nikon’s “LithoForum”. Companies such as Luminescent have developed software to calculate the optimal mask from a desired pattern, so called inverse lithography. I think these solutions are margin improvement strategies rather than node implementation options.
The simplest doubling approach is to expose, develop and etch twice, with 2 interleaved patterns that would potentially enable the 11 nm node with 22 nm equipment. Obviously the lithography costs are doubled while the density goes up as a factor of 4, so lithography cost per bit goes down 2x rather than the traditional – closer to 4 x. The cost advantage is not as good as it used to be, but there is still an advantage to a shrink. Success relies on very low defect density and excellent overlay. It’s worth noting that at 16 nm there are all the costs of doubling with half the density advantage so it’s close to a push from a cost per bit standpoint.
The logic guys are trying a rather different strategy by forcing the designers to lay out devices so that the logic patterns are as regular as memory, and then double pattern an X axis of regular lines and a Y axis of short cut lines. This could enable the 11 nm node for logic.
For memory at 11 nm, all the other doubling strategies are looking for ways to reduce the 2x cost penalty of each doubling cycle. The first strategy is sidewall doubling where the pattern is conformally coated and anisotropically etched to create free standing sidewalls. The X axis lines could be directly doubled, so that the cost would be closer to 1.5x compared to a single optical layer. If the pattern is irregular then all sides of all the features get doubled and a cut mask is used to trim the ends, and the costs will be between 1.5-2x. The comments at the conference suggest that defect density has been a problem for people who are trying this approach.
The doubling strategy that got most attention at the conference was Directed Self Assembly (DSA). I talked about DSA in detail in an earlier blog. DSA relies on directing the phase separation of block copolymers to “fill in” the spaces from a 22 nm pattern. Similar to side walls, one opportunity is to double the X axis regular lines. The DSA does not naturally migrate to irregular patterns. As I noted in my previous blog, there is a possibility for directing small groups of contact holes in logic and SRAM devices. The processing costs for DSA is probably slightly lower than sidewall as there is atmospheric deposition rather than vacuum, however this are new materials and processes so the defect risk is higher.
Both side wall and DSA could enable a further doubling, DSA has been shown to directly quadruple the seed pattern. Furthermore, DSA with 7 nm half pitch were shown at the conference. At 6 nm, even if the cut mask required at 3 patterning operations, the total lithography costs would be 4.5x the 22 nm node for a 9x increase in density. DSA is much more advantageous over sidewall for quadruple features.
MY CONCLUSION ON TRENDS IN ADVANCED LITHOGRAPHY – double patterning will enable future progress down to 11 nm node possible even the 6 nm node, with lower cost per bit than 22 nm node – just not as low as historically, and with the even multiple nodes 11 and 4 nm nodes showing better cost per bit. Once double patterning is established and the industry has learnt how to deal with it, past experience suggests it will become the incumbent and be difficult to dislodge.
The insertion opportunity for EUV or imprint is probably 6 nm node. Imprint might get an earlier insertion in NAND because of defect redundancy. I cannot see how multi-e-beam can be ready for HVM before the late 2010′s, where it could make an impact on foundries, and perhaps doing cut masks for the 4 nm node.
About the Author
Mike Watts has been patterning since 1 um was the critical barrier, in other words for a longtime. I am a tall limey who is failing to develop a Texas accent here in Austin. I have a consulting shingle at www.impattern.com.
My blog “ImPattering” will focus on the latest developments in the business and technology of patterning. I am particularly interested in trying to identify how the latest commercial applications evolve.