Advanced Semiconductor Device Lithography – what is going to happen next ?
by Michael P. C. Watts
The noise and hype level around lithography these days is rather loud. At SPIE’s Advanced Lithography conference this year, a huge crowd heard all the different strategies and opinions. Is there any way to make sense of all the confusion? This is my view !
To start, I think it’s worth remembering what has to be accomplished. The goal is to manufacture sub 22 nm node devices in volume manufacturing. Intel has made it clear that in order to commit the billions of dollars for a factory, they must have fully operational, final versions of all the equipment at least 2 years before node production. Only then can they have confidence that they can ramp defect density in the factory and deliver product on schedule. To me this means that the systems must be “post-beta”. Post-beta means that a customer has received the first operational tool that nominally meets all specs (beta system), run it for 6 months, found a bunch of issues, the supplier has fixed the issues and is shipping a “final” or post-beta tool. Given a 2 year node life, at the same time as the customer buys a device made with a new node, the post- beta systems for the next node must be being shipped. Do not forget that the customer has probably received pre-beta systems that do not meet all the nominal specs long before the “real” beta. They have used these systems for process development and validation. A cycle of learning in these systems is a minimum of 1 year; to design, build, debug and evaluate process. It’s worth remembering that 22nm = 22 nm memory half pitch and 44 nm logic half pitch. Memory can push the resolution limit because the patterns are highly regular.
As I write, the industry leaders are shipping 22 nm parts, receiving post-beta equipment for 16 nm node, and evaluating pre-beta equipment for 11 nm node.
Alright, so in this context, what was presented at Advanced Lithography this year ? It is best to start with all the alternatives and end up with the “only game in town” optical with double patterning. The alternatives are; EUV, multi-beam e-beam and imprint. Let’s start with EUV. Multiple pre-beta tools have been shipped, most with a Cymer light source. Cymer announced that they had demonstrated power sufficient for 30 wafers per hour, with upgrades to their pre-beta sources. Certainly 30 wph are enough to do real process development. They need another 3x to get to commercially viable cost of ownership for EUV. On the customer side, everyone – but EVERYONE is watching them and willing them to success, unfortunately the photons appear to be impervious to either guilt, stress, or financial reward.
MY CONCLUSION ON EUV – still pre-beta, needs a post-beta shipment of a 3x more powerful source within 2 years for 11 nm node. This might be just possible as there are relatively few integration issues, but they would have to show propotype success this year. Missing the 11 nm node, would require yet more complexity of higher NA or shorter wavelength to hit the 6 nm node.
Schematic of Cymer EUV power source, from www.cymer.com
Another alternative is multi-beam e-beam, Burn Lin from TSMC gave his usual energetic and entertaining pitch for the potential of multi beam and laid out the target performance and costs that these systems must meet. It’s clear that for foundries like TSMC, a maskless tool has a unique value proposition. The CEA – LETI group showed some nice 20 nm features from a Mapper system. The bad news is that the hard challenge for multi-beam, which is overlay, remains data free. CEA-LETI said that they are about to receive a pre-alpha tool.
The other leading developed is KLA/Tencor who are developing REBEL, a tool with a very compact column and 1 million beams. They use multiple columns exposing multiple wafers simultaneously to meet throughput targets, there is just the overlay to solve. It is certainly true that conventional e-beam has demonstrated excellent overlay, and offers the ability to map each beam. Interferometers are used to follow multiple columns and wafers. It seems to me that the real challenge is the distortion mapping of the multiple beams as they scan and thermal stability of these large multi-beam blankers and scanners. The stability will determine how often the beams need to be remapped. This sounds like an engineering problem rather than an invention, but it could take a long time to identify all the sources of overlay error and correct. From a schedule point of view they will have to go through pre alpha, alpha, and beta to get to a HVM tool. Two other groups showed initial patterning results for their feasibility demo systems.
MY CONCLUSION ON MULTIBEAM E_BEAM – none of the teams is even at a fully functional prototype. It seems to me that they have to be at least 4 years (2 nodes) behind EUV and imprint, there is so much work needed to reduce these systems to perfection. That just puts them at the 4 nm node at the earliest. It could still work for foundries who lag 1-2 nodes behind logic and memory leaders.
Molecular Imprints (MII) has argued that after 10 years of effort, they are the closest system to meeting all the targets for the next generation tool, and it is hard to argue with their numbers; <15 nm half pitch resolution, 1.2 secs per field or 30 wafers per hour exposure cycle, 10 wafers per hour throughput, 10 nm overlay, 10 defects cm-2 for 20 wafer runs. You can buy all this capability for what passes as a snap in the litho. business, roughly $10M systems delivering 20 wafers an hour. MII are getting valuable experience with 11 nm node patterning on patterned media today. There is still work left to get overlay down to low single digit nm and, more importantly, everyone (except MII and Toshiba) is skeptical that the defect problem is soluble. Toshiba is looking at imprint for NAND, a device that does have error correction and defect redundancy. At the conference, Toshiba announced electrical line yields for 10 meter long lines and defect data at 10 defects per cm-2. Not good enough yet, but they have been progressing at 10x improvements per year. So the question is – is this enough to motivate the industry?
MY CONCLUSION ON IMPRINT – MII’s partner could ship a beta HVM tool within a year, so could get to 11 nm node. Only Toshiba and Sematech have acknowledged running pre-beta evaluations of imprint. I still think that broader industrial support is going to be needed to get enough horsepower behind defect reduction. Full disclosure, I was part of the founding team at MII.
SUMMARY – Best case EUV and imprint could just make the 11 nm node but both have outstanding issues, the earliest e-beam could make is the 4 nm node.
All this leaves multiple patterning to extend optical lithography to the 16 nm node and quite possibly the 11 nm node. As we saw at the conference there are multiple paths which I will “simplify” down to; low k imaging, random interleaved double pattern, X&Y axis double pattern, sidewall frequency doubling, and directed self-assembly frequency multiplication. I will talk about these in my next blog.
About the Author
Mike Watts has been patterning since 1 um was the critical barrier, in other words for a longtime. I am a tall limey who is failing to develop a Texas accent here in Austin. I have a consulting shingle at www.impattern.com.
My blog “ImPattering” focus’s on the latest developments in the business and technology of patterning. I am particularly interested in trying to identify how the latest commercial applications evolve.
March 8th, 2012 at 12:29 am
It’s crazy that EUV requires a 20 kW laser, while ArF immersion laser only needs 90 W, from the SAME company! That’s >200X cost of ownership right there!
March 13th, 2012 at 6:22 pm
Despite its marketing-driven name change, EUV remains soft x-ray projection lithography (SXPL). It can seem to shake its birth wavelength or x-ray’s attendant problems, principally total cost per wafer. Despite its name change(s), maskless and multibeam remain e-beam direct write, with its attendant problems of throughput and data management. The new, shiny penny, directed self-assembly will suffer from the same disease that befell other pretenders to the throne, like ion beam lithography, SCALPEL, etc., which is “nice from far, but far from nice”. There simply isn’t enough time to debug it, scale it and build infrastructure. Some of us have been waving the OLF flag for nearly 20 years: optical lithography forever, certainly for advanced logic. Memory, particularly cost-driven NVM, trying to overtake HDD, might go imprint.
March 15th, 2012 at 3:32 pm
I checked with my friends at Cymer. The wall plug power for a ArF laser that generates 90 W is about 75 kW. They expect that the lasers for EUV will require about 3 x more wall plug power. Its all about the differences in efficiency.
March 22nd, 2012 at 5:43 am
Yes, the 20 kW CO2 laser @20% efficiency means 100 kW for EUV,
but the 90W ArF laser should be 1% efficient, or 9 kW for ArF immersion.
March 14th, 2013 at 8:18 am
There is a long lasting discussion on pseudo-multi-(e)beam DW concept boldly demonstrating that with having a large a number of conceptual feasibility gaps this approach has a very slim probability, if any, to yield a viable technology. See http://www.linkedin.com/groupAnswers?viewQuestionAndAnswers=&discussionID=97351367&gid=1874399&commentID=124684614&goback=.gmr_1874399.amf_1874399_8681861&trk=NUS_DISC_Q-subject#commentID_124684614)
March 14th, 2013 at 11:56 am
Well, it looks like nobody is brave enough to talk about the DPG associated matters and their critical significance for the (Pseudo) Multi-Beam DW concept.
Recently I was revisiting DARPA REBL program manager news release http://www.darpa.mil/Our_Work/MTO/Programs/Maskless_Nanowriter.aspx ) and found it important that it clearly states, probably for one of the first times, the following:
“A critical differentiating component of the Maskless Nanowriter concept is the use of a reflective electron beam pattern generator that converts design data for an integrated circuit into a column of 1 million parallel electron beams … ”
This reminded me my message to the REBL leadership I wrote when I was working for REBL: “The DPG chip is the most critical unit. For those who understand the matters, it became clear from the very beginning … that the DPG chip is the most critical and central unit, the heart of the whole REBL concept, requiring maximum attention and focused efforts to design and fabricate it. Not the column, and not the stage and not the gun, or whatever you were focused about was that important and critical as this small 1”x1” piece of silicon. No doubt the DPG chip is the most critical and central unit of the whole REBL project. ”
REBL is a heavily science-loaded development, requiring a team of well-qualified experts to lead it to successful resolution. But it is super critical to have talented leadership with adequate vision to foresee and wisely lead the team in a right, in most cases uniquely right, direction.
I do not want to comment on the current leadership vision, but under its management the REBL activities, and certainly funds spending, were focused on designing columns, and magnetic levitating rotary, and then linear stages, and whatsoever, and no proper attention was given to DPG design, and its fabrication and functionality testing. I think already significantly more than $200M was spent (and to my opinion wasted) by both DARPA an KLA, and they still do not have even a clue if the DPG conceptual functionality is feasible. Because the leadership was/is focused on making a costly litho machine.
The (Pseudo) Multi-Beam DW approach contains a huge and completely uninvestigated conceptual feasibility gap, – the DPG configuration and functioning, which is a real Pandora box, with so many “killer-snakes” inside, so scaring that I understand why the REBL leadership is hesitating even to openly discuss these matters.
Remember, the DPG is a pixelated chip, each pixel being configured as a multi-electrode well, e-beam reflection performance of which is extremely sensitive to within-the-well electrical field configuration, which in its turn depends on the state of the surface within the well, which in its turn is extremely sensitive to surface modification, contamination, charging, re-structuring, thermal conditions and a number of other factors. It makes no sense to start building even a simplified prototype without clearing
Here is just a short list of the DPG conceptual GO-NO GO issues which must be cleared prior to start building even a simplified litho prototype:
* Is DPG capable to sustain its functionality under the electron impact induced and high energy ion bombardment induced surface modification and erosion?
* Is DPG capable to sustain its functionality given its electrical (50-100 KeV) and inevitable thermal insulation and really significant amount of heat released during its fully functional activity?
* Is DPG capable to sustain its functionality given the well-known effects of surface contamination due to e-induced chemical deposition of the vacuum background gases.
Getting answers to these most critical questions does not require that complicated and multi-million expensive equipment, no columns are necessary, no greatly expensive levitating stages, and a small team of well qualified experts to carry out these really critical feasibility checks. Without having positive answers to these questions it makes no any rational sense to spend $$ for designing and building expensive HW, like HV-HV columns, MagLev or Linear wafer stages, or developing data transfer SW and so on, because if the DPG long term (at least 1 hour continuous and stable) functioning is not feasible the continuation of the development sounds like an obviously unjustified nonsense.
I am not in a position to consider what are the actual reasons (lack of vision, or luck of professional responsibility, or simply lack of knowledge and competency), which could explain the REBL leadership decision to start building expensive HW without having clear answers to these conceptual feasibility-defining questions
Also some other feasibility testing was just a MUST prior to starting promoting the idea of and constructing the monstrous staged columnarium, and it is associated with the impact of 0.5 W 100 KeV electron beams over the wafer itself and the product devices, because if the wafer is locally worped, or the resist is damaged, or the device functionality is affected, then the applicability of the DW EBL is absolutely not possible. And these tests are also very simple not requiring any sophisticated equipment, no columns, MagLevs etc., just very simple testing stands simulating exposure conditions and a couple of wafers from the partnership, say, TSMC to check the mentioned effects.
I guess, all this conceptual feasibility testing cost would not exceed $1M, and these MUST TO BE DONE feasibility tests had to be carried out first thing in the morning prior to wasting $100Ms on generations of columns, stages, supporting SW etc. etc.
Well, as I’ve mentioned above, it requires well-qualified and talented leadership having adequate vision to foresee and wisely lead the team in a right, in most cases uniquely right, direction.
No any proper testing of the its most conceptually critical, and full of unknowns device, the DPG chip, was actually carried out at the early stages of the REBL program and not even by now…
March 14th, 2013 at 12:02 pm
BTW, the concept abbreviation is REBL (from Reflecting E-Beal Lithography), and not REBEL