Michael P C Watts
Light Emitting Diodes (LED’s) are about to pick up one of the key drivers from the low cost IC industry – Gallium Nitride (GaN) LED’s are being manufactured on large silicon wafers. This opens the future prospect of manufacturing 300 mm wafers filled with LED’s at a huge cost advantage. The larger area means that there are many more devices per process operation, which has driven the semiconductor industry to larger wafers. A 300mm wafer will have roughly 10x as many chips as today’s 100 mm wafer. In addition, at 150mm, a silicon wafer for LED’s is about $40, as compared to $1500 for sapphire, a huge cost saving. GaN on Si is a significant development for both LED manufactures who will need to match the cost advantage, and to equipment suppliers who will have a new market for their Si processing expertise.
At Photonics West 2012 in San Francisco, a team from Osram described 150 mm wafer results, and a team from Samsung described 200 mm results. These papers are accompanied by a press release from Osram announcing a pilot manufacturing line. Both teams suggest 2-3 years to product sales.
The barriers to hetero- epitaxy, such as GaN on Silicon are significant. The reactive deposition chemicals must not attack the substrate, the dislocations caused by different crystal structure of the two materials must be eliminated, and the deposition occurs at high temperatures. These high deposition temperatures cause cracking when the wafer cools because of the difference in expansion coefficient. Osram’s academic partner described a 10 year program that has led to the latest success.
The Osram and Samsung groups described similar strategies, they use a complex array of buffer and blocking layers to protect the substrate, adjust for differences in crystal structure, block dislocations, and apply compression to the wafer that offsets the effect of cooling.
The high performance LED’s made on silicon had properties that match the ones made on their standard sapphire wafers. To date the Osram pilot line is running 150 mm wafers, but they also showed some initial results for 200 mm wafers. On the other hand , Samsung showed device results for 200 mm wafers, and showed flatness and defect density data for 200 mm GaN/Si that matched 100 mm GaN/Sapphire.
The blocking of the dislocations was particularly interesting. In previous blogs, I have talked about masking lateral overgrowth as having a potential to reduce dislocations and improve LED’s, and this year it appears that it is part of these pilot operations. However, both groups use non-continuous deposition rather than lithography to create a patterned layer (not supported by the Union of Concerned Lithographers !).
All in all, I thought that this was both a technically impressive achievement of a complicated engineering challenge and a potentially very significant commercial development. In my view, the fact that they built complicated state- of- the –art devices on these new substrates shows that they are dead serious about GaN on Si as a future technology. Bridgelux have also reported 200 mm GaN on Silicon but they did not present at this conference . The race is on as to who will be first and largest to deliver GaN on Silicon. There will be significant commercial reward to the winners.
About the Author
Mike Watts has been patterning since 1 um was the critical barrier, in other words for a longtime. I am a tall limey who is failing to develop a Texas accent here in Austin. I have a consulting shingle at www.impattern.com.
My blog “ImPattering” will focus on the latest developments in the business and technology of patterning. I am particularly interested in trying to identify how the latest commercial applications evolve.