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Blog review December 9, 2013

New blogs examine the future of NAND flash memory, a preview of the International Electron Devices Meeting (IEDM) – is it time to think about the end of silcon? – Skyworks’ use of SOI, the Sony ISX014 8MP sensor, MEMS and the Internet of Things, and The ConFab, which will be held June 22-25, 2014 in Las Vegas.

Design-for-Testability (DFT) Verified with Hardware Emulation

Several years ago, while at Automatic Test Equipment (ATE) leader Teradyne, I witnessed frequent debates on a fundamental dilemma: On the production/testing floor, is it better to pass a failing device or reject a good device?

Blog review July 21, 2014

New blogs discuss the best way to verify multi-IP, multiple power domain SoCs, contemplate what TSMC may have changed in 20nm devices from the 28nm generation, what happens when we run out of room “at the bottom” around 4nm, the recent EUV lithography workshop, presentations from The ConFab last month, and Qualcomm’s perspective on 3D integration.

Blog review July 14, 2014

New blogs give several different perspectives on Moore’s Law and the potential for continued scaling, the persistent uncertainty of EUV lithography, the VLSI Symposia and FD-SOI, and the recent Suss Technology Forum.

Blog review June 2, 2014

New blogs address the Internet of Things, which TSMC’s John Lin sees as the next big thing after mobile devices; Applied Materials’ new Volta system design around cobalt liners and capping layers; Soitec’s Christophe Maleville’s view on FDSOI; the recent SEMI 2.5/3D IC forum in Singapore; questions surrounding EUV lithography’s insertion into volume manufacturing, and the MEMS Industry Group’s Conference in Japan.

Blog review March 31, 2014

New blogs discuss metrology in the age of 3D memory, the many benefits of FDSOI, this year’s IMAPS Device Packaging Conference, the recent MEMS Industry Group meeting in Europe, and the upcoming R&D panel session at The ConFab in June.

IP interoperability in SoCs: Mix and match doesn’t always work

More often than not, a design re-spin isn’t just a simple re-spin with a tweak here and a tweak there. The new design will probably have to comply with modified specifications that inevitably raise the bar for performance and power usage, and it will probably contain new IP that must be integrated.

3D EDA brings together proven 2D solutions

Design methodologies and technologies for 2D multi-chip systems are extended into 3D using proprietary tools based on industry standards.

Blog review March 10, 2014

New blogs take a look The ConFab, where Dr. Gary Patton of IBM will provide a keynote talk, Applied Materials’ success working with Lawrence Berkeley Lab, ST’s view of FDSOI, the recent RTI- Architectures for Semiconductor & Packaging conference, the EUVL Conference during SPIE’s advanced litho program, and the newly-reported numbers for January: the best ever!

Blog review March 3, 2014

New blogs take a look at design challenges associated with re-filling an engineering change orders (ECOs), this year’s ISS meeting, and the pervasiveness of cheap silicon.

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