SMD: CEA-Leti has two major and separate programs, including one in directed self-assembly (DSA) and another in multi-beam e-beam. Let’s start with DSA. What is CEA-Leti doing in DSA?
Pain: For DSA, we have what we call the ‘Ideal’ program. We are developing 300mm processes. We have materials development with Arkema. Other partners include TEL and Sokudo. We are working with STMicroelectronics to transfer the technology from a process point of view. We are developing this capability for lab scaling to industry production.

SMD: What have you demonstrated with DSA?
Pain: We have demonstrated resolutions down to 18nm half-pitch, which is considered the 7nm logic node. We think we can extend PS-b-PMMA down to the 7nm node. The concept is to enable 7nm to 4nm resolutions with Arkema’s materials.

SMD: The big question is when do you think DSA will move into production?
Pain: From my point of view, it should be 10nm. You will start to see some demonstrations at 14nm.
Tedesco: You can ask me that in July. I still say 2014.

SMD: What are the challenges with DSA?
Pain: There will be some challenges in terms of defectivity and process maturity.
Tiron: For contact shrinks, the processes are here. It’s stable. That means you can absorb a lot of the variations with the block copolymers. But you don’t have pitch or density. If you move to contact doubling, you have the density. But you lose the process window stability. The placement of the contacts is also less certain. But what is important is now we have materials, processes and tracks. What we really need now is some real fabrication. The applications depend on the end-user. What we need is the end-users to tell us: ‘We need this and that and then move in that direction.’ That’s what is missing today.

SMD: What have you accomplished in your DSA process flow?
Tiron: We have implemented a process flow on a 300mm track, which comes from Sokudo. We have a complete DSA process cycle in one track. The track handles the brush coat and block copolymer coating. The track also has high temperature hot plates for block copolymer cure. We also worked with Sokudo to develop a PMMA removal process. We demonstrated different exposure treatments and solvents. What we are trying to do now is address contact hole shrinks and contact multiplication. With the polymers from Arkema, we are able to do resolutions from 20nm period, which means 10nm resolution, to 60nm period, which means 35nm resolution. Contact shrink is possible using both cylindrical and lamellar morphologies.

SMD: What about yield or defects?
Tiron: We have shown good uniformities with three sigma around 2nm. After the optimization of the process, we counted 6,800 divisional points on the wafer. We only found five missing contacts. By using block copolymers, we showed 99.93 % valid contacts on the wafer. This is just using PMMA.

SMD: Let’s move to multi-beam. What is CEA-Leti doing in multi-beam?
Pain: The second program is called Imagine. This program started last year. We have a partnership with (multi-beam e-beam vendor) Mapper Lithography. Other partners include Aselta, JSR, TOK, TSMC, Sokudo, Dow, STMicroelectronics, TEL and Mentor.

SMD: How far along is Mapper’s multi-beam tool?
Pain: The first machine will consist of 1,300 beams. The throughput is one wafer per hour. The tool will arrive the beginning of June. That’s targeted for the 14nm logic node. This machine will be interfaced with the Sokudo track. The first exposures will start in the last quarter of this year. Eventually, the target is to reach 16nm half-pitch. Our goal is to have 13,000 beams with the Mapper tool. We expect to scale the throughput from one wafer per hour to 10 wafers an hour. Then, we plan to push the resolutions down to 10nm half-pitch.

SMD: What is the cost-of-ownership for the Mapper tool?
Pain: The cost is 1 million euros for two wafers per hour. So in other words, that’s 5 million euros for 10 wafers per hour. Our eventual goal is to cluster 10 machines together. That’s 50 million euros for the cluster configuration.

SMD: Isn’t multi-beam taking longer than expected and behind schedule?
Pain: If you take the original roadmap, we are late. Some of the technical achievements have taken a long time.
Tedesco: One of the problems is there is a lack of support from the industry. It’s a shame that there is a lack of support, when you look at what’s being done on the EUV side. That’s one of the reasons that multi-beam is not mature yet. Of course, there is the technical aspect. TSMC, of course, is the one that is pushing this technology. But beyond TSMC, there is a lack of support. But I think the support will eventually come.

SMD: TSMC has stated it wants to do all layers with multi-beam. Is that practical or will multi-beam end up doing traditional direct-write applications like ASICs?
Tedesco: It could be a challenge to do all layers with multi-beam. But a maskless tool could be useful in terms of ASICs or prototyping. It’s ideal for the foundries. But the first applications for multi-beam will likely be contact holes and the cut layer.

SMD: How about STMicroelectronics? STMicroelectronics has been involved with direct-write for many years.
Tedesco: ST is a partner of Leti. So they are following Imagine very closely.

SMD: What about funding for multi-beam from the likes of Intel, GlobalFoundries and Samsung?
Tedesco: Good question. What we can say is that they are following us very closely. They know what we are doing. At this point, they are not part of the program.

At the moment, everyone is tired of interesting times, and those in the used equipment sector are no different. The current industry downturn has been one of the longest ones in recent memory for them.

It’s difficult to express how bad things have been in terms of numbers for the used chip equipment market. The sector is fragmented, and much of the buying and selling is between brokers—often for specific customers. But one thing is clear: Times have been tough.

“This has been the longest sustained downturn in the used equipment market in the 16 years that I’ve been in it,” said Julian Gates, managing director for AG Semiconductor Services. AG is one of the largest, if not the largest, suppliers of used semiconductor capital equipment and services in the industry.

“We’ve seen worse, but this one has been sustained for a long time and has had a real negative impact on everyone in the used equipment market,” Gates said. It is a sentiment voiced by others in the market, whether they’re based in the United States, China or Europe.

Even as some first-tier chipmakers are moving to add capacity, things are quiet among second-tier customers. “I haven’t heard of a second-tier scanner that was sold in the last three months,” remarked one sales executive from used equipment supplier SDI Fabsurplus LLC.

But there are signs of the proverbial light at the end of the tunnel. Just as there has been talk of capacity expansion in the chip industry, consequently there are signs the market for used equipment may be picking up. One of the few notable bright spots this spring for purveyors of refurbished semiconductor capital equipment and services has been in the packaging front, where 3D packaging and related newly-developing technologies are proving drivers in the chip industry as a whole. In terms of equipment, that means a need for wet processing, plating, physical vapor deposition (PVD), photolithography and etch equipment.

This technology-driven expansion is coupled with the fact that companies in the backend are also looking to move packaging and test operations to mainland China. The market for analog and power devices also has remained strong, as has demand for memory to some extent, all driven by consumer electronic devices. And all this has helped drive what business there is of late in the used equipment sector.

But as a whole the entire market, in terms of geography, is really quiet, used equipment providers say—even China, where the only projects of any notable size currently underway are being driven by the government, as opposed to the private sector. As one Fabsurplus sales executive tersely quipped of the Chinese market, “It’s not hot.”

But recently interest on the part of customers has picked up across much of the used chip equipment market. As one Shanghai-based equipment sales executive noted with regard to China and packaging, no one is doing through-silicon vias (TSVs) just yet, but everyone there is talking about it. Whether or not all this interest translates into actual orders in the latter half of the year remains to be seen. Historically, however, increased activity in the backend, i.e. packaging, usually presages a broader rebound, and used equipment vendors are cautiously optimistic.

“We are seeing definite signs of an uptick,” said AG Semi’s Gates. “For the first time in a year and a half, people are broadcasting their intent to invest. Our hope is that it will be sustained … and not just an initial hype that we see sometimes.”

He characterized this interest as potentially large expansions in Asia, Brazil and India, where companies are looking to invest in entirely new—to them, at least—manufacturing lines. North America and Europe are still quiet, he said, but these markets usually follow as interest builds elsewhere.

At least one used equipment company that is focused on the European market is anticipating an uptick of orders in Q4, however. Some European device makers are currently planning to convert fab lines to what is, for them, next-generation technology, said Tony McKie, CEO of memsstar.

UK-based memsstar is focused on the market for deposition and etch equipment and related support services for both semiconductor and microelectromechanical systems (MEMS) applications. McKie noted the company recently has done several wafer-size conversions for customers, upgrading fab lines from four- to six-inch wafer processing and from six- to eight-inch.

In terms of a Q4 uptick there are a number of standard pureplay semiconductor companies in Europe looking to place orders at the end of the year, but there has been keen interest in the MEMS market as well, not to mention power devices. “Right now we’re seeing quite a bit of interest in power applications,” McKie said, noting that European power device makers are seeing intense competition from Asian device makers at the moment.

Will used 300mm equipment represent strategic opportunities?
If the industry is on the edge of a current up-cycle, it also may precede interesting times in the next cycle, as the market for used 300mm equipment continues to develop. The market for refurbished 300mm tools is relatively small and new, compared to the used equipment market as a whole.

It’s also been busy, of late and will likely continue to be so. But refurbished 300mm tools are the sole province of first-tier IDMs and foundries, for the time being.

It’s no secret that capacity is tight at the leading edge and near-leading edge nodes, and yet companies need to shave costs wherever they can. This means demand for used 300mm tools at top-tier device makers—core systems that can be refitted or otherwise refurbished for other applications—has remained strong even as the market for used 200mm tools has been ghostly quiet for most of this year.

A primary example of this is financially beleaguered DRAM maker ProMOS’ sale of a 300mm fab in Taiwan earlier this year. Foundry giant GlobalFoundries snatched that up. “From what I’m seeing in their forecasts, GlobalFoundries is a major player,” said a FabSurplus sales executive. The foundry expects to buy some $150 million of 300mm tools and services in 2014, for both backend and frontend expansion in 300mm fab lines.

There just have not been any second tier chipmakers, be they IDMs or foundries, making a play or even expressing much interest in used 300mm tools—yet.

But what if there were? Could a second-tier chipmaker theoretically jump into a market dominated by first-tier players by upgrading a fabline with used 300mm equipment and consequently offer a cost-effective alternative product?

“If one of those second tier companies had decided to go after, say Promos facility … their cost of equipment capital would have been lower” than that of a company investing in a brand new fab line, said Gates. “We haven’t seen it happen, but that’s not to say it couldn’t. It’s really been the first-tier customers that have taken advantage of the 300mm equipment in the used equipment market,” he said, but noted that AG Semi has actually seen some tentative interest from second-tier customers.

Certainly it is a possible scenario for a European chipmaker. Memsstar’s McKie noted that European companies are well established and comfortable with manufacturing devices using refurbished 200mm tools; they would not be averse to adding 300mm capacity with used systems. The real issue is the availability of core manufacturing systems; as with Promos’ fab sale noted above, used 300mm tools tend to get bought up very quickly in today’s market.

So this scenario is highly unlikely in the current cycle—assuming that the industry is on the edge of an upturn. But it’s a distinct possibility in the next cycle. Perhaps with the low-power needs of the end market driving things such as finFETs in the front end and TSVs in the back end, there will be an opportunity for a second-tier player to jump into a market dominated by first-tier players as the 300mm market matures and more systems become available.

There is definitely interest on the packaging side for used 300mm tools, refurbished tool brokers report. Many 300mm packaging lines that utilize advanced technology will be moving from pilot lines into production in the next cycle. Could this be a strategic yet cost effective opportunity for a second-tier company?

It is speculation, to be sure, but one thing is certain: A growing market for 300mm tools will be a boon for used equipment providers. As markets mature, original equipment makers don’t always find it cost-effective to offer service and support for used equipment. This provides an opportunity not just to broker and sell used tools, but service and support for those tools as well. In terms of the 300mm market and the related manufacturing complexity found in the accompanying technology nodes, there likely will be a strong demand for refurbished and repurposed tools and accompanying support services in the next cycle.

“The used 300mm equipment market is really now just developing,” said Gates. “We’re really going to see it come into it’s own.”

3D stacked-die using through-silicon vias (TSVs) is on the slower path. Advanced chip-stacking has several challenges and is still a few years away from mass production. In contrast, 3D NAND is heating up, as Samsung and SK Hynix are accelerating their efforts in the arena.

Presently, NAND vendors are on the 2xnm or 1xnm nodes. The prevailing thought was that vendors would scale existing planar NAND at three distinct points down the 1xnm node. Typically, NAND vendors denote those points as 1x, 1y and 1z. Then, after the so-called 1z or 1znm node, planar NAND supposedly would hit the scaling wall, forcing vendors to migrate to 3D NAND.

In fact, 2D NAND will have difficulties scaling beyond 10nm. This is because the critical structure in NAND—the floating gate—is seeing an increase in the dreaded cell-to-cell interference in the word lines.

SanDisk still plans to scale NAND for two more generations until 2016, and then, it will debut 3D NAND. But in what appears to be a switch in strategy, Samsung and SK Hynix plan to develop 2D NAND at the 1x and 1y nodes. Then, “it appears that Samsung is bypassing 1z, similar to SK Hynix,” said Doug Freedman, an analyst with RBC Capital Markets.

Instead of going to 1z, Samsung and Hynix will move directly to 3D NAND. In fact, Samsung will begin sampling parts in the second half of 2013, with production slated for 2014, Freedman said.

“As there is maybe one more shrink left for planar NAND, some manufacturers are making the transition earlier to 3D NAND,” said Greg Wong, an analyst with Forward Insights. “Scaling of planar NAND is nearing its end, and 3D NAND is seen as the way to continue density increases and cost reductions for NAND flash memory.”

With 3D NAND, memory vendors also will move from a costly lithography-centric production environment to a less-expensive etch/deposition flow, said Gill Lee, a senior director and principal member of the technical staff at Applied Materials. “The overall cost of the tools will be cheaper with 3D NAND,” Lee said “This is mainly driven by the difference in the number of critical lithography and double-patterning steps.”

3D NAND contenders
Samsung will bring out 3D NAND first, followed in order by SK Hynix, Toshiba and Micron, Forward Insights’ Wong said. In 3D NAND, Samsung hopes to leapfrog the competition and grab the early profits with its so-called terabit cell array transistor (TCAT) architecture.

In TCAT, NAND layers are stacked using an oxide and nitride deposition process. Then, the nitride is removed by an etch process. Finally, the bit and word lines are created using a tungsten fill. TCAT and other 3D NAND architectures are different than 2.5D/3D stack-die technologies, where devices are stacked and connected using TSVs.

Another NAND vendor, SanDisk, has a different strategy. “SanDisk is planning to remain planar until 2016, while competitors begin to develop and produce 3D (NAND) into the market late this year and early next,” said RBC’s Freedman. “SanDisk’s (3D NAND) solutions are being judiciously developed to cater to the high-performance market. The high-performance side of the market will not be ready to qualify 3D for another two to three years.”

Using 193nm immersion lithography, the SanDisk-Toshiba duo is producing 19nm planar NAND with a 19- x 26-nm cell size. Then, at 1y, SanDisk’s goal is to devise planar NAND with a 19- x 19.5nm cell size, with production slated by the end of this year.

Then, unlike Samsung and SK Hynix, SanDisk will scale planar at 1z. “There is no need to rush into 3D” until it is cost effective, said Ritu Shrivastava, vice president of technology at SanDisk. In reality, 2D NAND will remain the mainstream technology for some time. Over time, 3D NAND will move into high-end applications, like solid-state storage.

By 2016, SanDisk hopes to debut the Bit Cost Scalable (BiCS) technology, a 3D NAND technology that was originally conceived by Toshiba. BiCS makes use of a “punch-and plug” structure. Toshiba has fabricated a prototype 32-Gbit BiCS test array, with a 16-layer memory cell based on 60nm design rules.

The advantage of 3D NAND is that it doesn’t require leading-edge lithography. Going to 3D NAND will present some challenges, namely the development of quality parts with good read/write performance with endurance. “3D NAND will require a different equipment set,” Shrivastava said. “The burden will shift from lithography to deposition and etch.”

3D NAND process challenges
It also will present NAND vendors with some difficult decisions. First, despite their public roadmaps, vendors may be forced to migrate to 3D NAND sooner than later. “Most leading-edge producers are doing 2D NAND manufacturing at the 20nm or 19nm node, which is the last generation of self-aligned double patterning technology,” Applied’s Lee said. “By using self-align double patterning, one can pattern about 19nm or 19.5nm half-pitch.”

But for some time, the problem with 2D NAND has been apparent—it is running out of steam. “With existing planar NAND, there is not much room to squeeze in the materials for the charge-trap flash or the floating-gate,” Lee said.

In theory, NAND hits the wall at 10nm. “In order to scale NAND manufacturing beyond that, the industry must adopt self-aligned quadruple patterning or self-aligned triple pattering,” he said. “That allows for 10nm half-pitch. But doing 10nm half-pitch patterning will be extremely difficult. It will add a lot more process steps, which will increase the cost of manufacturing.”

Clearly, 3D NAND is the future based on two factors: scaling and cost. “If you compare the cost between sub-20nm planar versus 3D NAND, I believe it will be a lot cheaper to build a 3D NAND fab,” he said. “Planar is driven by litho. In 3D NAND, the bit growth is enabled by increasing the number of vertical layers. This has nothing to do with litho.”

3D NAND can be produced using existing 193nm lithography. Other expensive steps, such as self-align double-patterning etch and low-temperature atomic layer-deposition (ALD), are also eliminated. All told, 3D NAND is largely dependent on two technologies: deposition and etch.

The big challenge is to enable high-aspect ratios using new etch techniques. “There are three distinctly new etch processes in 3D NAND,” Lee said. “This includes high-aspect ratio memory hole etch, which did not exist in planar NAND. There is also a high-aspect ratio trench-line etch, which also did not exist in planar. And then another one is a so-called staircase etch. This is a very long process, which has to provide the landing pads for the contacts.”

3D NAND also introduces alternating stack deposition, which defines the vertical stack. In a 32-layer NAND device, for example, the process could involve some 64 layers of deposition, plus some dummy layers. All told, the flow requires some 70 alternating deposition steps. “The existing tools cannot provide such high productivity,” Lee said. “So that involves a new type of chamber design and technology.”

Metrology is also a critical part of the equation. “Nanometrics believes that 3D NAND will use 20% to 25% more OCD tools relative to planar NAND,” said Weston Twigg, an analyst with Pacific Crest Securities.

“In planar NAND, the gate width is defined by lithography,” added Applied’s Lee. “Now, the gate width is defined by deposition. So, the uniformity of PECVD deposition of each layer, and the quality of the films, are very critical. When we deposit several layers, it’s not a big deal. But let’s say we deposit 40, 50 or 70 layers in-situ. That means we have to control the surface of the interface very smoothly from the beginning. Otherwise, we end up with a rough surface on the top, which will not work.”

So far, Micron, Samsung, SanDisk-Toshiba and SK Hynix have yet to discuss the exact specifications for their respective 3D NAND devices. It’s unclear how many layers the initial devices will have, prompting many to ask a simple question: How far will 3D NAND scale? “I see it going for several generations,” Lee said. “But after 3D NAND, the industry will require another breakthrough.”

The so-called Global 450 Consortium (G450C) also has set a goal to bring 450mm fabs into high-volume manufacturing at the 10nm or 7nm nodes by 2018. That gives the industry a little less than five years to develop the production tools for 450mm fabs, which are expected to cost a whopping $10 billion or more. Based in Albany, N.Y., the G450C has five members—GlobalFoundries, Intel, IBM, Samsung and TSMC.

But between now and 2018, there is a staggering amount of work to be done. Based on the current progress for select equipment, fab technologies and standards, the path towards 450mm will be a bumpy road and it’s unclear if the industry can meet the 2018 target.

The most obvious problem is lithography. For example, ASML Holding is not expected to deliver a production-worthy, 450mm version of its extreme ultraviolet (EUV) lithography scanner until 2018. Other challenges include lithographic cost-of-ownership and throughput.

On the wafer-processing front, Applied, Lam, TEL and others are moving full speed ahead in 450mm. TEL also is proposing an “open platform” standard—a move that has received a lukewarm response. Meanwhile, there is some movement in metrology, as a new consortium has recently been formed to address the challenges in 450mm.

And the industry is still debating over various 450mm fab standards, such as aisle space and ceiling height. There is even a debate over the type of cranes needed to install 450mm tools. Other standards, such as gas interface boxes, cooling water manifolds, and hookups for power, are also in the works.

That’s just the tip of the iceberg. The goal for the G450C is not only to help develop these technologies, but it also has the arduous task of getting the various players to synchronize on the roadmap. “It’s going to require a collaborative and concerted effort to introduce (450mm technology) in an efficient manner,” said Steve Johnston, director of external programs and technology strategy in the Technology Manufacturing Engineering Group at Intel, at a recent SEMI event. “All of this requires flawless and synchronized execution across the industry and at multiple levels.”

Avoiding past mistakes
Indeed, the industry hopes to avoid past mistakes. In the mid-1990s, the IC industry wanted to make the shift from 200mm to 300mm fabs. The equipment industry had the 300mm tools ready in the late 1990s, but chipmakers pushed out their 300mm fabs amid an IC downturn. Equipment vendors ended up holding the bag and lost a fortune. Shortly thereafter, chipmakers began to ramp up their 300mm fabs, but the events left a bad taste in vendors’ mouths.

Recently, Intel, Samsung and TSMC have been pushing for 450mm fabs. The argument is that the industry needs to make a wafer transition every 15 years to stay on Moore’s Law. Moving to 450mm wafers will give chipmakers a 2.25x boost in wafer area and a 30% cost reduction, according to chipmakers.

For some time, however, fab tool vendors were lukewarm about 450mm. There are only a handful of customers who would buy 450mm tools, and it’s unclear who will foot the R&D bill for the technology.

More recently, 450mm has become a reality. Intel and TSMC have outlined plans to build 450mm fabs. And in 2011, the G450C was established at the College of Nanoscale Science and Engineering’s NanoTech Complex. The G450C recently opened a cleanroom. Its roadmap also calls for 450mm pilot lines in 2015 and 2016, with high-volume production targeted for 2018.

“Synchronization and collaboration are very important to avoid the same type of issues we ran into in the late 1990s with the transition to 300mm,” said Kirk Hasserjian, corporate vice president for the Silicon Systems Group at Applied Materials.

There are other issues, namely supply-chain readiness, return-on-investment and R&D funding. “The (R&D funding) issue requires a very different business model,” Hasserjian said. “That has not been completely resolved. We have the consortium activities, which have provided some level of funding.”

Fab tool challenges
The industry has moved to fund at least one technology, namely lithography. Intel, Samsung and TSMC recently invested in ASML, in an effort to accelerate ASML’s efforts in 450mm and EUV. And with separate funding from Intel, Nikon is developing a 193nm immersion scanner for 450mm.

ASML itself has initiated 450mm programs on two separate platforms and four wavelengths, including EUV. The goal is to deliver “early version tools” in 2015 to 2016, with 450mm production systems due out by 2018, said Jim Koonmen, general manager of Brion Technologies, a division of ASML.

The development of a 450mm EUV scanner is expected to be a herculean effort. Today, ASML is struggling to deliver 300mm EUV tools amid delays with the power sources. Cost is also an issue, as ASML’s pre-production EUV scanners cost $100 million or more per unit today.

Throughput is also an issue. The throughput for a 450mm scanner in general is projected to be only about one-half of a 300mm tool, Koonmen said. A 300mm tool has a throughput of about 250 wafers per hour (wph), while a 450mm system can run 100-125 wph at 1.1x the cost, he said.

“If you look at the entire semiconductor process, there are steps that do get a lot of leverage from larger wafer sizes and can realize cost reduction,” he said. “Unfortunately, with lithography, there simply isn’t that much of a benefit in going to larger wafer sizes. We are scanning as fast as we can. The number of fields is going to increase when we go to larger wafers, but that just means your throughput for each 450mm wafer is going to go down. So you’ve got double the number of fields, but you are going at half the throughput. That in itself is not easy to do. In order to handle a 450mm wafer, you need to have larger stages with larger masks, and that creates a whole bunch of issues for us.”

Meanwhile, amid the problems with EUV, the industry is hedging its bets by developing 193nm immersion scanners for 450mm. Optical is a proven technology, but the solution is expensive. At 10nm or 7nm, chipmakers must also use expensive multiple patterning schemes.

Delivery schedules for 193nm immersion are more certain, however. “450mm is expected to be in production by 2018,” said Hamid Zarringhalam, executive vice president at Nikon Precision. “We will ship development tools earlier than that.” By 2015, Nikon plans to ship “early learning tools” based on 193nm immersion for 450mm, Zarringhalam said. Nikon has already garnered “multiple orders” for the systems, he added.

On the wafer processing side, there are also some technical and cost challenges. “Prices could rise 30% to 50% for 450mm tools, as they did when the wafer size shifted to 300mm from 200mm,” said analyst David Motozo Rubenstein, who is also the author of a blog entitled “Chips and Dips.”

Applied, Lam, TEL and others are developing standalone 450mm tools. TEL also is proposing the idea of having an “open and modular platform” for 450mm. This would enable fab tool vendors to develop various plug-and-play process modules for the open platform, thereby reducing costs and development times. TEL and its rivals could develop modules for the platform. “The open platform is a concept for the 450mm high-volume manufacturing era,” said Aki Sekiguchi, vice president and general manager for SPE marketing at TEL.

The open platform could benefit smaller companies that don’t have the resources to develop standalone tools. But larger companies are not eager to endorse an open platform, because it will give its rivals a competitive edge. “We are looking at it,” said Applied’s Hasserjian. “We are not doing what TEL is doing and advocating a modular platform.”

Metrology challenges

Another challenge is the development of 450mm metrology gear. “There are not many companies that can invest six years in advance,” said Menachem Shoval, chairman of Metro450, an Israeli-based consortium that is developing 450mm metrology technology. “Even without going 450mm, there are huge challenges for metrology in terms of going down from 22nm to 14nm to 10nm to 7nm.”

This is especially true when moving from today’s planar devices to finFETs at 22nm and beyond. “Going to 3D has created numerous challenges for us,” said John Allgair, senior member of the technical staff at GlobalFoundries. “We see tenfold measurement problems as we go to 3D. A lot of things you see in 2D tend to get amplified as we go to these 3D structures. Then, we see some real challenges when it comes to compositional analysis. In finFET devices, we’ve got compositional measurements like SiGe with a percentage of germanium and a percentage of boron on a 3D structure. That’s a very complex measurement. Finally, we try and do measurements on test structures. The test structures don’t always mimic what’s actually taking place on your device. That really adds to the complexity of trying to manufacture finFETs in a stable manner.”

One solution to the problem is to collaborate through a consortium, Metro450′s Shoval said. Last year, for example, the Metro450 consortium was formed by the following companies—Applied Materials, Nova, Jordan Valley, Nanomotion and Intel. The group also consists of four universities in Israel, with some 60% of the funding coming from the Israeli government.

“Each company develops its own technology,” Shoval said. “They are competing with each other. But we can collaborate on those parts which are common. We will work on platforms, but not on detection.”

One of the goals for the Metro450 group is to meet the design rule targets by 2017. It is also devising technologies that are 2.5x faster than 300mm, thereby meeting the cost requirements for 450mm. To reach its goals, the group is working on five specific technologies: wafer handling; sampling optimization; wafer damage and contamination; calibration; and data processing.

“We plan to complete our work in three years,” Shoval said. “So companies will still have about three years to complete the development of their high-volume manufacturing tools.”

But as Bassilios Petrakis, director of product marketing for test products at Cadence pointed out, “[Test] is not in fashion, but when we hit one of those brick walls then suddenly we have to think how we are going to solve it. You’re on autopilot until you hit a disruption, and 3D represents a disruption.”

Whether it is memory stacked on logic, which is most common today, or stacking multiple logic die on top of each other vertically with through silicon vias (TSVs), both approaches are complicated and require more infrastructure than traditional SoCs.

Yervant Zorian, a Synopsys fellow and chief architect, noted that we have always dealt with multiple chips—but the multiple chips that we dealt with previously were packaged chips. “Having packaged chips on a board allowed us to test the chips fully upon packaging when they are on the wafer. And also, after being packaged to give the full quality chip, proven and warrantied to the board-level team to assemble it on the board. Now that’s all good when a die is packaged—a package protects it from further defectively. However, with 3D stacks or 2.5D interposers or some other advanced packaging technologies we are dealing with there is bare die that is unpackaged so the whole issue starts with that.”

So even though the bare die are fully tested, they are prone to defectively during assembly, mounting, transportation. “Whatever you do between the production of that die up through the time it is assembled with the rest of the dies there is this defectivity magnet situation where certain things happen to it and therefore we need to retest it after it’s been assembled—whether it is two dies, four dies, at every stage you need to test it again to make sure that nothing is damaged,” he added.

Clearly, the test challenges with stacked die include the need to test things at multiple points during fabrication and assembly, Petrakis said. “Then there is a big question about how much testing is required. With test there is cost and what do you forgo and what do you actually test.”

There are two schools of thought here, he noted. One is to use the normal manufacturing test type of approaches such as implanting test circuitry as is normally done and testing each die separately. “You make sure that you apply all the tests and then you know you probably have good die to work with. ‘Probably’ is a good term because you never know.”

Then, if the design will use through-silicon vias, what is the best approach to test and how do you get access to the test interface? “On a normal chip you just go to the pads and you say, ‘These are the test pads,’ and you target those. On a TSV-based design there is a lot of talk about landing probes, but the dimensions are so small that there is fear that they are going to be damaged,” he added.

It’s not all doom and gloom with stacked die, though. “The fun comes in when you start stacking logic die,” asserted Stephen Pateras, product marketing director for Mentor Graphics’ Silicon Test Solutions group. “In the case where you had a single logic die you had full access to it. If there were any test pins and memories that needed to be accessed directly even though they are stacked, you’re going through the BiST, the JEDEC standard interface, so you don’t have to worry about accessing the DRAMs directly. But with stacked logic die, now presumably you want to test pieces of a logic die. You want to test the interconnect between them, so you need access each of those logic die independently somehow. Generally you don’t have access to them, because if they are stacked vertically the idea is that the bottom die will be the one that is connected to the package and the other die are connected to each other. So there may be neighbors top or bottom in that stack. That’s where we need to have a way of going through the stack to get access to those die for test so you need some kind of test access architecture that makes use of the TSVs.”

At the foundation of such a test access architecture is the proposed IEEE P1838 standard, which gives just such access.

Zorian explained that IEEE P1838 complements the work that was done previously with JTAG 1149.1 and IEEE 1500, whereby JTAG was for the chips on the board and 1500 was for the cores in the SoC. “P1838 is for the dies in a 3D structure to talk to those dies. You need an access port and this access port cannot be JTAG. It cannot be 1500, but it can be something between the two and very complementary to those working hand-in-hand coherently with the first two standards to handle the new multi-dies in a package. P1838 will allow us to know exactly what that test bus is. The seven-bit communication bus proposed today will communicate the test related functions between one die to the other, from that die to the next and so on.”

By the time 3-D becomes prominent it is expected that P1838 will be ratified as an IEEE standard.

Further, Cadence’s Petrakis noted that the idea behind p1838 is isolation. “How do we isolate one die from the others such that we can test it internally without disturbing anything else? Then it’s not quite really disturbing it. It’s really a matter of true isolation. You do not want any foreign signals or unknown traditions to affect the testing that you are doing. The isolation is that we put the chip in a mode where it only sees data coming in and out from itself. In other words, the application of test reading the results back is not influenced by anything else.”

The looming cost concern
Amidst the technical challenges of 3D and 2.5D stacked die is the discussion surrounding who will pay for all of this extra testing.

Synopsys’ Zorian said, “The two stops in test that we used to have, which is testing the chip at the wafer level and testing the chip post-package, will still be there. But now we introduce intermediate steps so suddenly we need to do more test in between. When I have two dies together, three dies together—these are the prevalent situations where we need to test them. And there is a cost associated with it because it is after the die has been produced, so you cannot cost-wise expect the die producer that is the chip manufacturer to do that. It is a packaging-oriented cost because it happens later on during the stages of pulling those dies together. It depends who will be doing it and therefore who will pay for it.”

At this point, it seems that the cost will not fall to the die producer, but it depends on how the business model develops—especially because several chip manufacturers and foundries have expressed interest in being part of this ecosystem. “Whether it is TSMC, GlobalFoundries or otherwise, if they are doing it then of course it will be the last stage, because it’s not the wafer manufacturing stage or the wafer testing stage. It is one stage after that.”

However the situation turns out, the rising wave of 3D manufacturing and test is causing ripples throughout the entire ecosystem.

The last big gold rush occurred around 2008, when more than a dozen foundries jumped into the bipolar-CMOS-DMOS (BCD) market to capitalize on the booming power-management sector. Now, the next gold rush is centering on an emerging technology—the radio frequency (RF) silicon-on-insulator (SOI) market.

Today, IBM, STMicroelectronics and TowerJazz offer RF SOI foundry processes for the merchant market. Over time, analysts estimate that a dozen or more foundries could offer RF SOI. Altis Semiconductor and Grace Semiconductor have announced plans to enter the RF SOI fray. Two others, Lapis Semiconductor and Silanna, have put RF SOI on their foundry roadmaps. And sources indicate that GlobalFoundries, MagnaChip and TSMC are developing RF SOI or evaluating the technology.

Foundries are jumping on the RF SOI bandwagon amid a boom for select parts, particularly within the RF front-end for the latest smartphones and tablets. Typically, the RF front-end consists of power amplifiers (PAs), RF switches, tunable capacitors and filters. Generally, the PA and switch are based on gallium arsenide (GaAs), while the tunable capacitors and filters use various technologies.

RF SOI and its variant, silicon-on-sapphire (SOS), recently have made inroads for the RF switch—at the expense of GaAs. Most PAs are still based on GaAs, but the tide is slowly turning. For example, Peregrine Semiconductor is developing an SOS-based PA for a future smartphone at Apple, according to RBC Capital Markets.

Generally, RF chipmakers make GaAs-based devices in their own fabs. Chips based on RF CMOS, RF SOI and SOS generally are outsourced to the foundries. RF SOI is not a difficult technology to develop, but the real issue is that the sector could meet the same fate as BCD. As it turned out, the BCD market was not big enough to support a dozen foundries, prompting a shakeout in the arena.

In all likelihood, there is room for only a handful of RF SOI foundry players. “I would say IBM and TSMC are the only ones that have the economies of scale (in RF SOI),” said Doug Freedman, an analyst at RBC. “IBM is the leader in RF SOI right now, with TSMC trying to play catch-up. There are some other vendors like TowerJazz in the market, as well.”

From a supply/demand perspective, there is already ample RF SOI capacity to meet demand right now. “I have heard that capacity in RF SOI is adequate,” said Christopher Taylor, an analyst with Strategy Analytics. “I would have my doubts about the prospects of serious shortages barring compelling information to the contrary. Also, in light of the fact that RF SOI does not really push into the CMOS, small-node frontier, there is potentially quite a bit of capacity available from older fabs and foundries at the higher nodes.”

Rushing into RF SOI
The stakes are high, especially as RF content continues to increase in the latest mobile devices. In total, the PA market is expected to grow from $1.7 billion in 2008 to $3.8 billion by 2015, according to RBC. The multi-throw RF switch market is projected to grow from $262 million in 2008 to $1.2 billion by 2015, according to RBC. And the tunable capacitor market is expected to reach $500 million by 2016, it said.

“Driving this growth is rising handset and tablet units, which requires a greater amount of PA ICs,” RBC’s Freedman said. “Principally driving (RF switch) growth is rising radio bands. Driving (tunable capacitor) growth is the wider frequency range of bands and the need to reduce antenna size without performance trade-off.”

There is also an increase in design complexity amid a transition from 3G networks to the next-generation, 4G/LTE wireless standard. “LTE and carrier aggregation are thorny problems even in the best of situations,” said Michael Noonen, executive vice present of global sales, marketing, quality and design at GlobalFoundries. “You also want to be as Spartan as possible in the RF front-end design from a battery consumption standpoint.”

GlobalFoundries, which has been expanding its RF process offerings, is “very much interested” in RF SOI, Noonen said. “We have a lot of experience with SOI, but there are also other approaches in RF,” he said.

Indeed, OEMs face a series of complex device and process choices. For years, GaAs has dominated the RF landscape. GaAs has a larger energy gap and is faster than silicon, but it is more expensive to manufacture. RF CMOS, RF SOI, SOS and silicon-germanium (SiGe) are also in the mix. The RF version of SOI combines CMOS with a highly-resistive, thick-film SOI substrate.

RF SOI is an alternative to GaAs, with equivalent insertion loss and noise isolation characteristics. RF SOI also enables OEMs to integrate various chips on the same die. Another technology, SOS, makes use of an insulating sapphire substrate. And SiGe is built with silicon transistors to create RF circuits.
Meanwhile, after years of promises, RF SOI and its variants are finally cracking the RF front-end. OEMs are moving from GaAs pHEMT to RF SOI and SOS for the RF switch, said Paul Boudre, chief operating officer at Soitec, an SOI wafer supplier. “GaAs pHEMT will not disappear, but it will remain for more specific devices,” Boudre said.

Actually, the buzz started when Apple incorporated Peregrine’s SOS-based RF switches in the iPhone 5. Samsung’s Galaxy S4 and other smartphones are also using SOS-based switches, according to RBC. SOS is a proprietary technology that is only offered by Peregrine. Its SOS chips are made on a foundry basis by Lapis, MagnaChip and Silanna.

Rodd Novak, chief marketing officer of Peregrine, said SOS has better insulating properties than RF SOI. SOS also uses sapphire wafers, making it a more expensive than RF SOI. But the overall cost for SOS is declining. This is because sapphire wafers are ramping up in high-volume markets like LEDs, which will impact the cost of SOS, Novak said.

Peregrine recently rolled out a new version of SOS, based on 0.35-micron technology. “Before, we grew an epi (layer) on top of our sapphire process,” Novak said. “Now, we are taking a very clean silicon substrate and bonding that to the sapphire. That process enables better performance.”

Apple to drive SOI?
The fact that Apple and other OEMs have adopted SOS and RF SOI for the RF switch has given the technology some credence. It also has caused a stampede of foundry players looking to enter the RF SOI sweepstakes.

Now, with help from the foundries, RF chipmakers are looking to displace SOS-based switches with traditional and less-expensive RF SOI technology. “RF switches are typically based on GaAs pHEMT, SOS and SOI, with SOI gaining more and more market share away from the other and more expensive technologies,” said Marco Racanelli, senior vice president and general manager at TowerJazz.

In addition to cost, OEMs are also interested in capacity. In one effort to ensure supply, IBM recently signed a second-source foundry deal for its 0.18-micron, RF SOI process with Altis.

Besides the RF switch, the next big market for RF SOI and SOS could be the PA, with Apple emerging as the possible driving force. “We believe that Peregrine is developing a unique integrated PA solution that is targeting the next generation of Apple’s PA product needs,” said RBC’s Freedman. “(This) could add approximately $1.25 in content, assuming (Apple integrates) five to six single PAs in 3G smartphones. We note that in 4G, PA content opportunity rises to approximately $3.00 due to rising single chip PAs per device.”

In another example, Qualcomm recently rolled out the RF360, an RF front-end that includes a PA based on SOI. Today, however, the jury is still out for PAs based on RF SOI and SOS. For the PA, GaAs still has a higher power-efficiency over CMOS.

Still, the handwriting is on the wall for GaAs. “For the PA, SiGe BiCMOS has strong market share in WiFi, while GaAs HBT has strong market share in cellular. RF CMOS is relegated to the very low-end 2G/2.5G cellular space,” TowerJazz’ Racanelli said. “SOI for the PA is only in R&D and may not deliver the best performance by itself. But combined with switches and other functions, (SOI-based PAs) could become relevant as new architectures are adopted. Our view is that SiGe has the best tradeoff in performance. The cost structure is closer to CMOS/SOI. SiGe is likely to gain more ground in the future.”

Also in the RF front-end, there is a tunable capacitor, which tunes the antennae to boost efficiencies. Peregrine is selling SOS-based tunable devices. Paratek and STMicroelectronics are selling components based on barium strontium titanate (BST). And WiSpry is offering a MEMS solution.

“There are two vectors worth exploring here,” GlobalFoundries’ Noonen said. “If you can do something in CMOS, it will be done in CMOS. We will see other ways to approach the problem. Using a tunable capacitor based on MEMs, for instance, you can attack the problem from an entirely different angle.”

Indeed, in the RF front-end, there is no one-size-fits-all technology; OEMs likely will adopt several types of chips and processes. “We will also see more functionality in the RF subsystem,” Noonen said. “The idea is to bring RF into more of a mainstream technology.”

SMD: What does hybrid metrology accomplish in the process control flow?
Allgair: The structures are becoming so complex. You are trying to measure a particular application on a 3D device, where you have a lot of variations that already took place prior to the measurement step. Hybrid is one of the ways to address that challenge. For us, it enables us to use a lot of the information that is collected upstream for the measurement event you are actually doing. It allows us to understand, as much as we can, about the structure in terms of how it was processed and what it looks like prior to that measurement step. And then, for the variables you are trying to measure, it helps reduce some of the uncertainty of those variables you may not understand from that particular process step you are measuring. Again, that information can be thickness, compositional and CD.

SMD: Do you think directed self-assembly (DSA) will succeed? And does the industry have an inspection/metrology solution for DSA?
Allgair: As we keep driving litho, there is a decent chance that DSA will happen. We will probably try to postpone it as long as we can, and try and get through what we’re currently using. When it does happen, it may end up being a different type of solution than we thought. After SPIE, and looking at one of the papers from MIT, it looks like there might be a way to measure the structures that were used to pattern your DSA. It might be that we monitor that structure. Then, we will have some confidence that the DSA activity takes place and works. All told, if we can get a DSA system that works well, and there is a cost advantage to it, that could drive an earlier adoption for DSA. That is a big component to DSA.
Heidrich: We certainly see the promises. The cost reduction is there, but the challenges of proving low defectivity and performance still remain. Certainly, in the case of memory and related types of processes, where you have redundancy, DSA will get adopted earlier. There has been work on contact holes, where you can do reduction with DSA. When the yield is proven, and if the cost benefit is there, DSA will get adopted. But I think that is still quite a few years away.
Newcomb: DSA is just one of the options available. We have all been in the industry long enough to know there are multiple options. But DSA is the one you want to try to avoid as long as possible because there are many unique challenges. Will it happen? Maybe not. If it does, you have to put all of the pieces together to bring it into high volume production. The challenge comes down to defectivity and integration.
Shetty: DSA is exciting. DSA will most likely happen, but cost would be the biggest challenge in terms of making it production-worthy.

SMD: The industry is in need of new inspection/metrology breakthroughs and tools. Do you agree? And how does the industry fund the development of new tools when there are not enough R&D dollars?
Allgair: It is apparent that we have a need for some new techniques. The ones we’ve talked about are multi-beam e-beam inspection, CD-SAXS, helium ion and a higher resolution CD tool. These are addressing defect-inspection resolution, CD resolution, scatterometry and compositional analysis. The problem that we are trying to grasp is the people that use these new tools are the ones on the leading edge. Those are for devices at 14nm and beyond. There are not a lot of companies in that space. So, it’s not clear how many tools would get ordered at the leading edge. And the other problem is chipmakers like GlobalFoundries, Intel and others may not have provided a clear and concise message in terms of what our future tool needs are to the toolmakers. Regarding GlobalFoundries, as well as my peers at Intel, TSMC and others, we all need to get a little better organized in terms of defining our problem statement to the tool vendors. The second piece is how do you fund a new tool development program? That one is challenging. We’ve seen other funding models, where we have joined other companies and put money together to drive the development of a new tool in litho or to drive a consortium. It’s possible that chipmakers can get together and try to drive something along that line. Another possibility is that each customer could buy the first generation of new tools from vendors. That might be enough for suppliers, who can then seek funding on their own.
Heidrich: We see two things that are challenging from the R&D point of view. One is the rapid consolidation from our end-customer base. We have fewer than a dozen major customers left. In the near- or long-term, that number will likely get smaller. So you have to have fewer customers to absorb the R&D for all the products you need to develop. Secondly, we have very diverse and complex process flows that different customers are adopting. This could be a finFET flow, vertical memory flow, or a 3D device integration flow. So you have more demands on your R&D. Right now, we need to make sure the R&D dollars solve the hard problems and we leverage that learning across all the different end customers. What that means is that if someone has a unique challenge, it gets harder and harder to provide a custom solution.

SMD: What about VC-backed startups like Qcept?
Newcomb: If you go way back, the industry had lots of startups. You had tier-one customers of course, but you also had a plethora of tier-two and tier-three fabs in the world. Now, as an equipment maker, you are not going to get funding that easily, because there are maybe 12 or less major customers in the world. It also takes more money to develop products. The dynamics are also different. You have new memory and logic requirements. We are tying together the OSATs and fabs with 3D TSV integration. In addition, the industry is moving towards two major suppliers on the equipment side and a handful of customers on the device side. That dynamic makes it very difficult. The big challenge is how will the industry keep investing and address those types of needs?

SMD: What’s the solution to this problem?
Newcomb: In one possible solution, companies on the device side could pre-buy the technology rights to the first tool to help fund some of the required investment and R&D. Or maybe, we can better integrate the university work into a model that can be funded and driven into the industry to solve a problem.
Shetty: R&D is becoming expensive. The device nodes are shrinking quickly. And customers’ expectations are increasing. Across the industry, everyone is pushing to get a lower cost-of-ownership and higher productivity. That’s just a fact of life. There are maybe 12 customers out there. But between the joint ventures and consortia, there are maybe four or five R&D centers out there. Today, it is very important that you are involved with these R&D fabs very early in the process. Then, the tool evolves with the process. So when customers move into production, the tool is already mature and ready to go. On the other hand, the devices are changing so much. And in a lot of cases, the customers themselves don’t know what’s going to happen.

One of the more difficult choices involves the less glamorous, but arguably the most critical part in a handset—the radio-frequency (RF) front-end. Typically, the RF front-end often comes in a module and includes various key components, such as the power amplifier (PA), antenna switch and filter.

The latest RF front-ends are moving towards multi-mode, multi-band PAs, based on the traditional technology for PAs—gallium arsenide (GaAs). The new PAs handle more frequencies, but it’s still difficult to support all 40 LTE bands; the RF front-end would end up being too big and costly. So for practical purposes, a 4G handset generally is configured with a different RF front-end to support various bands in a specific region, a sometimes complex and cumbersome process for OEMs and carriers alike.

But now there are some new options in the mix, which could help solve the band fragmentation problem for LTE and also turn the RF market upside down. One vendor, Peregrine Semiconductor, has been sampling a PA based on a variant of silicon-on-insulator (SOI) technology called silicon-on-sapphire (SOS).

And looking to accelerate the deployment of LTE, Qualcomm recently unveiled an RF front-end device, based on a mix of bulk CMOS and SOI. Instead of using an RF module, Qualcomm’s solution is housed in a package-on-package (PoP) configuration, enabling OEMs to save board space and re-configure the device more easily for a given region.

Multiple sources indicate that Qualcomm’s RF front-end incorporates the industry’s first multi-band, multi-mode PA based on SOI. Qualcomm declined to comment, saying the company isn’t ready to break out the technologies within the device. But after dissecting Qualcomm’s device, analysts said the part poses as a potential threat to GaAs-based PA suppliers, such as RF Micro Devices, Skyworks, TriQuint and others. “Qualcomm fired the first shot across the bow,” said Eric Higham, an analyst at Strategy Analytics, a research firm. “The subsystem consists of an antenna tuning IC, an envelope tracking (ET) IC for Qualcomm’s PA and a multi-mode, multi-band CMOS PA fabricated using a silicon-on-insulator substrate.”

Christopher Taylor, an analyst with Strategy Analytics, added: “This does not mean the death of GaAs, but the Qualcomm announcement undoubtedly signals faster acceptance of CMOS PAs. To stay competitive, GaAs PA suppliers will have to continue to innovate, and they may also need to offer their own CMOS PAs for the most cost-sensitive phones, as Skyworks and RFMD have already done.”

All told, there are some dramatic changes taking place in the RF front-end, where CMOS, SOI, and SOS are making inroads at the expense of GaAs. “GaAs has been displaced by SOI in the switch,” said Rodd Novak, chief marketing officer of Peregrine. “The PA is the next thing to conquer. The stranglehold that GaAs has on the power amp will start to erode.”

RF complexities for LTE
The stakes are high in the RF front-end, a $5 billion business, according to Strategy Analytics. The big market is LTE, a technology that boasts data rates of up to 100 megabits per second, which is up to 10 times faster than 3G. In total, there were 88 million connections on LTE networks in 2012, but this number is projected to jump to 322 million in 2013 and 1.6 billion by 2017, according to the firm.

LTE could grow even faster, but in many respects the technology is being held back amid a slew of challenges, namely the band-fragmentation problem. Today, there are four frequency bands in 2G cellular networks and five for 3G. “Right now, there are about 40 cellular LTE bands in total when you add 2G, 3G and 4G worldwide,” said Peter Carson, senior director of marketing for Qualcomm. “And so the challenge in terms of getting to scale in an LTE device, meaning the ability to design one device and be able to ship it anywhere, is really a function of how many bands you have in LTE.”

The problem is that many countries support their own LTE frequencies, making it difficult for handsets to provide coverage for all 40 bands. “Each country has its own frequency challenges,” said Shane Smith, vice president of mobile devices global marketing at TriQuint. “So, you are dealing with multiple bands in each country at a 3G level. This proliferates in LTE. And then with global roaming, (the bands) can’t interfere with each other. And that’s where the RF complexity is significant.”

In another example of the complexities, AT&T uses Band 17 and bought some spectrum in Band 4 for LTE. Technically, the two bands are not contiguous. But AT&T has implemented carrier aggregation techniques to make them look contiguous. “That’s the benefit and advantage of carrier aggregation, but that causes the RF architecture to change (to meet) that new requirement,” Smith said.

Generally, the 2G and 3G cell phone is relatively simple. Chipmakers ship an RF front-end, which includes a discrete PA that would support a particular band. In contrast, OEMs face some difficult choices with LTE. In theory, OEMs could build a “universal” handset that could support all LTE bands, but that could be large and expensive due in part to the RF content, screen size and other features. “You would be paying a lot of extra cost for bands that may or may not be used,” Smith said.

In a more practical scenario, OEMs can develop “regional” phones that support limited bands in a given region. But still, the question is how much RF content does a “regional” handset require? It depends on the type of handset and price point. As a rule of thumb, Smith draws the line at four bands. A handset that requires four or more bands may need multi-mode, multi-band PAs, while cheaper discrete PAs are suitable for a phone with anything less than that.

“Of all the smartphones shipped this year, the average band count is actually still less than four. Some 60% to 70% of the market would probably lean towards a more discrete solution, whether that is a discrete PA or putting two power amps in one package,” he said. “Some 30% to 40% of the market would take advantage of multi-mode, multi-band PAs. The ones shipping today would probably (support) six to seven bands. Then, on top of that, they also have discrete PAs, which can be populated or de-populated depending on the region they want to support.”

OEMs face other complex choices. To date, the PA has been dominated by GaAs. Now there are some new and emerging PAs based on CMOS, SOI and SOS, all of which promise to provide more integration and have lower power than GaAs. What’s next? “The RF antenna switch is moving from III-V materials to SOI,” said Paul Boudre, chief operating officer at Soitec. “GaAs pHEMT will not disappear, but it will remain for more specific devices.”

Soitec sees a surge in its RF business, where the company develops substrates based on bonded silicon-on-sapphire (BSOS) and high-resistivity SOI. “Our technologies’ market penetration in smartphones and other RF-based communication devices proves that our engineered substrates are competitive,” Boudre said.

GaAs is still a better solution for the PA, TriQuint’s Smith contends, but SOI still has its place. “All of the traditional RF manufacturers have SOI designers and are making many of our switches in SOI,” Smith said.  “SOI has better insertion loss and some natural linearity aspects due to the materials that GaAs pHEMT switches could not meet very easily. The SOI performance actually meets or exceeds (GaAs pHEMT). And there is a cost advantage.’’

The new contender

Leveraging the benefits of bulk CMOS and SOI, Qualcomm recently rolled out the RF360, a front-end solution that combines a PA, antenna switch, antenna matching tuner and an envelope power tracker. Supporting all seven cellular modes, the RF360 also works in conjunction with Qualcomm’s digital cell-phone chipsets.

Qualcomm integrated the PA and antenna switch into one device. “What we tried to solve here is what we call the LTE band fragmentation problem,” Qualcomm’s Carson said. “The integration of the PA and antenna switch frees up the board area so you can have enough space for the filters, duplexers and additional switches to support roaming bands, and have a single design that can be shipped to any market.”

Another key is that the device comes in a PoP package, which cuts board space by 50%. “It allows (OEMs) to have a faster development cycle,” added Steve Brown, senior director of product management at Qualcomm. “By just changing the top of the PoP package, you can actually have a different set of characteristics in bands for a given region and phone.”

The RF360 is based on both CMOS and SOI. “It’s a mix-and-match of SOI and CMOS,” Brown said. “What we’ve done is look at each of the various areas and look at the best way to get to the highest levels of integration.”

For PAs, many argue that GaAs has a huge power-added-efficiency (PAE) advantage over CMOS. Brown dismissed that notion, saying CMOS and SOI are indeed ready for LTE. “You can actually use CMOS for very complicated RF front-end solutions. For example, we have a GSM, UMTS, CDMA and LTE front-end all on one piece of silicon,” he said.

Another key to Qualcomm’s PA is a technology called envelope tracking. In this approach, the voltage is constantly adjusted to make sure the PA is operating at peak efficiency. “PA efficiency is a challenge,” Carson said. “You don’t want to waste power and generate heat. Those two things are critical to smartphone design because you want to preserve battery life. If you don’t do something like envelope tracking, you actually waste power.”

Qualcomm’s rivals are keeping a close eye on the company’s new RF solution. “Do I think it’s a competitive threat long term? Sure,” said TriQuint’s Smith. “But I also think the CMOS solutions are not superior in performance to GaAs (for the PA).”

Qualcomm already dominates the cell-phone chipset business. Many OEMs may want to differentiate their RF front-ends and not get locked into using both Qualcomm’s chipset and RF solution, Peregrine’s Novak said. In any case, Qualcomm’s solution is a step towards bringing out the long-awaited single-chip, monolithic RF front-end. But it’s unlikely that OEMs will see a single-chip RF solution anytime soon due to cost. “The RF architectures are also changing so quickly,” Novak added.

With the move to the 20nm manufacturing node, double patterning (DP) became a requirement. In addition, topology changes occurred that demanded very regular structures, marking a significant departure from 28nm design. As a result of this new approach, new errors are popping up, such as DP violation loops, odd cycle violations and anchor path violations.

Certainly, double patterning was the biggest change and the biggest concern on the designer’s minds when they began moving to 20nm, observed David Abercrombie, advanced physical verification methodology program manager at Mentor Graphics. They wanted to know what double patterning was and how to deal with it.

“Also, for the foundries themselves, they wanted to know how were they going to find provide a solution that was viable to the users,” Abercrombie said. “That’s certainly been the bulk of the questions we’ve gotten with the move to 20 nm and below—things related to double patterning, finding and fixing errors, how to deal with parasitic extraction or LVS or whatever, place and route and other things associated with double patterning. It’s certainly a new and different kind of error to deal with.”

The nature of the difference

Most design rule checks typically are associated with either a single polygon or its neighbor. That includes width or spacing or area, which can be complex. For instance, the space is dependent on the width, the run length, etc., but it’s still basically a neighbor-to-neighbor interaction or the layout of the shape itself.

“With odd cycles and anchor path errors, it’s now an issue of the network of interacting shapes—multiple shapes that can be spread over long distances and how they interact with each other in the network of spacings to form this odd cycle or this anchor path,” said Abercrombie. “It’s very different than the traditional rule in that sense. In some ways people have learned to think about it more like an antenna rule that is network-based. It’s not conductivity-based, it’s spacing-based, but it’s about the network of shapes and the spacings.”

This is a whole new level of complexity for designers to deal with. “If you’ve seen 20nm designs from customers, they’re different from 28nm and the reason for that is because of the core fundamental issue in double patterning of conflicts, where one defines a conflict as a native conflict or a loop conflict,” said Manoj Chacko, product marketing director at Cadence noted. “A native conflict is something that you can detect but cannot fix without a design change. That means the designer has to make a design change.”

Consider a loop conflict, for example. If you have four polygons, for example, and two masks for double patterning at 20nm, then each polygon is split into two masks and four polygons is split into eight. That works fine in a very regular layout, but not all layouts are so regular.

“This seems kind of reasonable given that you can assign four polygons eight colors, but in reality it’s a little different because it depends on the proximity of the polygons to the others and so on,” Chacko said. “If you had nine polygons because of an L joint, for example, even if you have to split four into eight but the eighth polygon is not straight, it’s an L—now the L basically may become two colors again, making nine. This is called a loop problem, where you have the eighth polygon that is split into 2 colors. This is the problem that designers see. It doesn’t require systematic changes but it does require identification of the loop, and then there are methods to fix it.”

One other problem is when you think of that last ninth polygon as an L, where at the corner of the L where the two lines join. That could make a split. The foundries decide on the split based on their process. They may not do a split at a joint. They may do it on a straighter edge. But when they make the joint, there is an overlay of these two masks. If you think of that ninth polygon – that eighth polygon that got split into two pieces—they will expose first one joint, then etch it, then expose the remaining portion of that L, then etch it. Now you have to make sure these two exposures make that one L that the customer wants. The idea is that the overlay is a problem. In manufacturing, it’s called overlay. In design, it’s called stitching—meaning they have to make sure there’s enough overlap at the split/splice location. So that is another issue that design tools have to give good feedback about.

These coloring issues are exactly why Mentor Graphics looks at this differently, Abercrombie said. “Displaying the error as a ring is so much more productive than showing the colors because this was the initial mental struggle [with double patterning,] and the request that came up most was, ‘I want to see the colors.’ That was the first thing designers said—only the colors. And I said, ‘Why do you want to see the colors?’ ‘So I know what to fix.’ Seeing the colors is actually a misleading thing. If you imagine an odd cycle there is no legal way to color it. That’s the problem. That’s why it’s an error. There is an odd number of things interacting, and you have two colors and you can’t divide and odd number by an even number or you get a remainder. So you can’t color them alternating colors in an odd cycle, because somewhere in that cycle you’re going to end up with the same two colors next to each other. When you ask the tool to show you colors, inherently the tool can only show you the wrong colors because in that configuration there are no legal colors.”

A second problem is that there are many, many different wrong colorings that could be shown because there is no right one, so the selection of which one to show is completely arbitrary.

This is why Mentor approaches this type of error with a ring scenario. “By showing colors, there could be a random chance that I showed you that one error that may be the hardest one to fix and hence I’ve pushed you down a path of most work,” Abercrombie said. “By ignoring the colors—not showing the colors, if at all possible because it’s just going to mentally push you in a direction—look at the ring and look at the options that it is showing you as a benefit. Now you have multiple choices and you can do what is best for you.”

Not so scary

Mentor’s Abercrombie asserted that as scary as it is for designers to learn something new, “like anything else once they start dealing with it they learned pretty quick and they found it’s not those it’s not as overwhelming as they thought.”

And there are even some nice things about double patterning errors, he said, in that although the error can seem large and involve a lot of shapes with a lot of spaces around things, the advantage of it is that you have multiple options for fixing it. In a given odd cycle, for example, you only have to break one separation within the network of polygons that are interacting and it is clean. You don’t have to fix them all. You only have to fix one of them.

“In that way a single error has many ways to fix it and that’s better than a lot of other DRC rules,” he said. “When the check is like ‘me and my neighbor’ and how far away we are—when you only have one option you’ve got to fix that space and that may be difficult because of the ramifications of trying to fix it. When you try to move those edges, or you might have to move vias and other shapes, that could be a very complicated location to fix. But with a DP error, the fact that it’s got multiple options gives some freedom to say, ‘Here’s an odd cycle with five different spaces and there are actually five choices that I can make.’ I can look at which one is easiest for me.”

Saleem Haider, senior director of marketing for physical design and DFM at Synopsys, agreed. “[DP errors], at the highest level, look pretty much the same as a general design rule error. Even without double patterning at 28nm we have a fairly complex set of design rules that the foundries gives us and design implementation has to adhere to those. Ten years ago, pretty much all design rules were somewhat width- and spacing-oriented. Now the rules are very, very complex. Some of them are based on the size of the object itself, and there are spacings from corners and edges and sides, etc., so it’s a fairly complex set of rules.”

Double patterning becomes a part of that, so at the end of the day, a DP violation or a DP error is going to, generically speaking, look just like a design rule error, he said. Just as if there was a design rule error in the design, the foundry would not accept that design because when the design comes into the foundry, one of the first things they do is run design rule checking on it to see if it meets the checking criteria that they specified. If the design doesn’t meet it, they will send that design back to the design team. It’s part of the incoming process. It’s the same for DP.

Like many new technologies, understanding double-patterning errors is just a learning process, Mentor’s Abercrombie concluded. “The foundries first had to figure out what it is they want to provide and support and work with us to make the tool capabilities to do that. Now that they’ve rolled out the decks to the customers it’s been more about educating the customer to overcome that initial shock of something new and get them educated. As soon as they play with it for a little while, it comes pretty fast. They’re smart. For the ones that have already made that move, they are settling in pretty quickly.”

Additional resources:

http://www.mentor.com/solutions/foundry

http://semimd.com/mentor/

http://www.synopsys.com/Tools/Implementation/CapsuleModule/ic_validator_wp.pdf

http://www.synopsys.com/Solutions/EndSolutions/20nmdesign/Documents/20nm-and-beyond-white-paper.pdf

3D is a catch-all phrase that includes a range of new architectures, such as finFET transistors, 3D NAND and stacked-die using through-silicon vias (TSVs). Although a few 3D-like devices have appeared in the market, many chipmakers are still developing these technologies and face several process control challenges.

“In our industry, a lot of segments are metrology-limited,” said Christopher Bencher, a member of the technical staff at Applied Materials. “Overlay metrology is the number one area where we are limited. There is also a challenge with 3D devices like finFETs and 3D NAND. You have to be able to characterize them in 3D.”

As with many fab tool markets, there is a disconnect between the rhetoric from chipmakers and equipment vendors. Process control tool vendors insist they are ready for the 3D era. In contrast, chipmakers say many of the existing metrology solutions are running out of steam.

For example, some 50% of the process steps in a fab are devoted to inspection and metrology alone. About 10% of those steps use the workhorse metrology tool in the fab—the critical-dimension scanning electron microscope (CD-SEM). With finFETs, the CD-SEM is being stretched to its limits. “Three quarters of the steps can be handled by a conventional CD-SEM,” said Eric Solecky, senior manufacturing engineer at IBM. “This percentage is growing. It’s that fraction for 3D information that we don’t have a solution today for an image-based tool.”

Near term, there are other challenges in process control. “The main gaps in general are next-generation defect inspection, next-generation charge particle imaging, and next-generation scatterometry profile metrology,” said Benjamin Bunday, senior technical staff member at Sematech. Longer term, the industry also lacks a process control solution for graphene, carbon nanotubes and directed self-assembly (DSA).

Metrology madness
Several tool types—AFM, CD-SEM and OCD—can handle most requirements for today’s planar chips. Atomic force microscopy (AFM) uses a tiny probe to enable measurements. The CD-SEM is used for top-down measurements. And used for CD and overlay, optical scatterometry (OCD) measures the changes in the intensity of light.

But the process control world changed in 2011, when Intel rolled out the industry’s first finFETs. Using a transmission electron microscope (TEM), Chipworks recently discovered that the traditional one-to-one ratio between structures and transistors doesn’t apply with Intel’s tri-gate technology. In fact, one transistor can have multiple fins—six or more—while one fin can have multiple transistors, according to Chipworks.

So for finFETs, a given metrology tool must measure and characterize the separate pieces in the structure, such as the gate, fin height, sidewall angle and others. Each of those parts also requires one or more separate measurements.

The question is which single metrology tool can handle all requirements for structures such as finFETs and 3D NAND? The answer: None of them. There is no silver bullet. “We are already in a deluge of data,” said Jason Osborne, senior systems design engineer at Bruker. “We’ve got many systems making multiple measurements on the same structures and not getting the entire answer off any one system.”

In one possible finFET metrology flow, the fin is measured by the CD-SEM or AFM, and then, the results are feed to the OCD tool. Another possible metrology flow involves the CD-SEM, OCD and a TEM. The TEM, a system that shoots a beam of electrons through a tiny specimen, is used to validate the OCD model. “What you are trying to do is make your scatterometry model more robust,” said John Allgair, senior member of the technical staff and Fab 8 patterning metrology manager at GlobalFoundries.

Intel, meanwhile, uses a combination of undisclosed tool technologies within its finFET process control flow. “We need all solutions,” said Adam Schafer, area manager of metrology and inspection at Intel. “We need to combine them.”

In process control, the biggest challenges for Intel can be summarized in three words—cost, noise and throughput. “Noise is one of our top problems. And it is really distinguishing the signal from the noise in any one of our techniques,” Schafer said.

Each tool type has its own set of issues. “If you are talking about CD-SEM, my CD measurement is traditionally top down. That’s not enough. I cannot control my processes with those CDs,” said Alok Vaid, senior member of the technical staff at GlobalFoundries. “Regarding OCD, it’s a solution, but it’s too complicated. So if you look at 14nm, 10nm and beyond, I don’t think the small dimensions are an issue for OCD. In fact, it can work in your favor. The problem is correlations.”

For AFM, the challenge is to measure finFETs in 10nm to 20nm spaces and characterize the profiles and shapes, he said. “We can’t leave optical tools such as ellipsometry out of the picture. Since everything is going 3D, now you want to measure those thicknesses and compositions on actual 3D structures,” he said.

The solutions
For some time, GlobalFoundries and others have been talking about the solution to the 3D problem—hybrid metrology. In this approach, separate tool technologies are used in a flow. The challenge is to put rival tool vendors in the same flow and tell the competitors to collaborate and share proprietary data with each other. “Let’s take an example. You have a CD-SEM supplier. You have an OCD supplier. And let’s say you want to overlap them and get my results. You can’t do that unless you get those guys to draw an algorithm together and get them to collaborate,” Vaid said.

While hybrid metrology is perhaps the wave of the future, tool vendors are also improving their respective technologies. For example, using Applied Materials’ CD-SEM, IBM conducted measurements in a theoretical gate-all-around finFET with silicon nanowires. In this experiment, “you see nice defined edges, even when you are beyond the resolution image,” said Ofer Adan, managing technology and marketing manager at Applied Materials. “So can we go beyond 14nm? What this work tells me is that a CD-SEM can go down to 6nm on a gate-all-around device.”

This is not to say the CD-SEM can handle all finFET requirements. “It cannot see whether or not there is an undercut. We need to work together with the OCD guys,” Adan said.

Overlay is another challenge and OCD is being stretched to the limits. KLA-Tencor recently unveiled a dimensional metrology system, which includes a new OCD technology based on a laser-driven source. “We think this is an inflection point for scatterometry,” said Andrei Shchegrov, director of advanced development at KLA-Tencor. “Our signal-to-noise gets a huge boost across a very wide range of wavelengths. We found the increased sensitivity due to the light source allows us to see things we couldn’t see before. It allows us to measure deep structures like high-aspect ratio 3D NAND flash.”

Despite the breakthroughs, the industry is still searching for new and better 3D metrology solutions. There are some promising candidates on the table. For example, a possible successor to the CD-SEM is helium-ion imaging. And X-ray scattering (CD-SAXS) could succeed OCD.

“The CD-SEM today, for the most demanding applications, cannot resolve 3D information,” said IBM’s Solecky. “So the question is, ‘Do you need 3D information on the smallest features?’ The answer is yes. Potentially, helium ion is the solution.”

Helium ion enables 3D images, but the technology also can damage a device. The industry is looking for ways to tweak the helium ion microscope, which would make it somewhat comparable to the CD-SEM. “Technically, this involves a lot of challenges to make (helium ion into) a CD-SEM kind of tool. Those are not unsolvable problems, but it requires a lot of investments,” said Bipin Singh, product manager for Zeiss, a supplier of helium ion scopes and other fab tools.

As a replacement for OCD, the industry is looking at CD-SAXS, an X-ray scattering technology based on a synchrotron radiation source. “If you want 3D structures, you can certainly do it with CD-SAXS,” said Joseph Kline, a materials engineer at NIST. “The main limiter for CD-SAXS is throughput. Most of the measurements with CD-SAXS are done with a synchrotron source. Clearly, we are not going to have something like this in the fab. We are trying to figure out how to get a new source and make it work.”

There are other major gaps in metrology. For example, the current buzz in lithography centers on DSA, but it’s unclear if the industry has a metrology solution. “Metrology needed for DSA is really not different than the metrology needed for the rest of the industry,” said Applied’s Bencher. “You need to measure the registration of the holes. Now, when you are defining all of your holes by a mask, things tend to shift systematically, at least within the mobile region of the wafer. So how do you obtain an overlay measurement when things on the local level are shifted randomly? That’s not clear. It requires a different way of thinking.”