First of three parts: What’s missing, what’s running out of steam, and best guesses for how to tackle issues at future process nodes.

Second of three parts: Litho challenges; thinner resists; overlay and process effects; finFETs; stacked die.

Last of three parts: Hybrid metrology; debate over directed self-assembly; new inspection tools; shrinking R&D dollars.

Second of three parts: the future of e-beam and maskless; nanoimprint; DFM’s role in double patterning; a growing emphasis on collaboration.

First of three parts: The future and current state of EUV, ArF, nanoimprint, DSA, and direct e-beam; how much will the next node cost; where will the development money come from.

Last of three parts: EUV’s road map, venture capital, silicon photonics, directed self-assembly, and multipatterning.

First of three parts: Process control, variability, lithography, materials, stacked die, Moore’s Law and 450mm wafers.

Second of three parts: FinFET yields at different process nodes; controlling variance; differences between finFETs at 14nm and 10nm; SOI vs. bulk CMOS.

Last of three parts: 450nm wafers; the effect of industry consolidation; TSVs; finFETs; stacked die; fully depleted SOI.

First of three parts: What’s done and what’s missing from the supply chain; how good are the tools; 2.5D vs. 3D; test issues; the role of standards and where they do and don’t exist; what will drive demand and when.