Fairchild Semiconductor closes two facilities; Intel releases new packaging technologies, Thinnest-possible semiconductor material; New metrology tools from KLA-Tencor
Podcasts Videos Webcasts Archive
Silicon wafer shipments increase; The growing semiconductor industry in India; Equipment book-to-bill ratio remains steady; Next-generation smart glasses in development
Global semi sales hit record high; Benchmark established for EUV; Semiconductors for health and fitness set for double-digit growth; Smart cities on the rise
Gigaphoton achieves 92W EUV light source output; New graphene substitute has HVM potential; SMIC and Qualcomm collaborate; Nanolab Technologies acquires Microtech
Inpria completes another round of financing; GS Nanotech to launch mass assembly of 3D TSVs; memsstar relocates; Entegris launches i2M Center
Entropic consolidation; Field-effect transistor research, 2014 Symposium on VLSI Technology; ON Semiconductor to acquire Aptina Imaging
Fab equipment spending increase; SID announces winners of Display Industry Awards; Samsung’s 14nm finFET process technology ready; Synopsys, Intel and ST collaborate on 28nm FD-SOI for SoC design
STATSChipPAC releases new encapsulated wafer level chip scale package; Applied Materials reveals the Endura Ventura PVD system; Ziptronix and EV Group achieve submicron post-bond alignment accuracy on 300mm DRAM wafers; World Semiconductor Council agree on a series of proposals for semi industry
Increase in first quarter wafer shipments; Changes to the top 25 semiconductor suppliers; IC Advanced Technology Research Institute; The 17th annual IITC held this week
STMicroelectronics licenses 28nm FD-SOI to Samsung; DoD policy to reduce counterfeit semiconductors; OLED market growth; Applied Materials releases new CVD system
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The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.
EUV will introduce unwanted patterning distortions that must be accurately modeled and corrected.
How to tame data file sizes, address fractured data files creation and streamline data review techniques.