Semiconductor revenue report; Equipment manufacturing sales forecast; Soitec’s new eSI substrates; Cellphones projected to pass PCs as largest electronic systems market
Podcasts Videos Webcasts Archive
John Blyler interview Stephen Pateras, Product Marketing Manager of Mentor Graphics
Micron’s new processing architecture; Seoul Semiconductor’s next generation LEDs; Thin films out of semiconductors; Book-to-bill ratio above parity
Robert N. Noyce award recipient; Changes in the Top 20 semiconductor supplier ranking; ST wins Company of the Year; Tosoh expands to meet 450mm needs
imec demonstrates III-V finFETs; Rubicon launches large diameter sapphire substrates; the flexible display market growth; SRC’s RF research
Toshiba’s new embedded NAND on 19nm process tech; ASU photovoltaic research; LEDs key drivers in bulk GaN market; Managing legacy fabs
SRC’s new hybrid bio-semi research program; Book-to-bill ratio; 3D integrated capacitor research; Lab-on-chip research
Soitec’s COO Paul Boudre talks about the competitiveness of full-depleted planar with full-depleted finfet; capacity issues for SOI in light of ST’s open foundry model; and growth of High Resistivity SOI in the RF implementation on smart phones.
Researchers discuss their projects at SRC TECHCON 2013. William Song, Georgia Institute of Technology
NY’s Marcy Nanocenter to launch “Nano Utica”; Semi materials market; Touchscreen panel sales; Analog and digital ICs
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The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.
EUV will introduce unwanted patterning distortions that must be accurately modeled and corrected.
How to tame data file sizes, address fractured data files creation and streamline data review techniques.