Cypress and Spansion complete merger; Strong fab equipment spending forecast for 2015; 11 IC product categories to exceed total IC market growth in 2015; Global mobile phone display module shipments signal stronger competition among manufacturers
Podcasts Videos Webcasts Archive
NXP and Freescale announce merger; Semiconductor Industry Association announces highest January sales ever; UT Dallas research could lead to affordable night vision and thermal imaging; Breakthrough in OLED technology
Top R&D spenders announced; Applied Materials unveils 3D CD SEM metrology tool; Smartphone display panel manufacturers face pressure to reduce prices; Semiconductor unit shipments forecast to reach 1 trillion units by 2017
imec announces DSA process technology breakthrough; GlobalFoundries and imec announce partnership; January book-to-bill released; Samsung announces mass production of mobile application processor using 14nm finFET process technology
Slow progress on Applied Materials-Tokyo Electron merger; Silicon wafer area shipments increased 11% in 2014; SEMI wins semiconductor etch equipment export control ruling; One-atom-thin silicon transistors hold promise for super-fast computing
Semiconductor industry posts record sales in 2014; SEMICON Korea opened this week; ClassOne Technology acquires two product lines from Microprocess Technologies; Cambridge Nanotherm appoints new non-exec director
Solid growth in automotive semiconductor market; $4M grant to UMass Lowell for printed and flexible electronics development; Book-to-bill ratio below parity; Researchers use oxides to flip graphene conductivity
SUNY Poly announces founding president; Solving an organic semiconductor mystery; UC Berkeley Extension announces new semiconductor IC program; 2015 tech trends and drivers
Blue LED research shines light on manufacturing problems; SEMI World Fab Forecast data shows favorable DRAM growth; The technology that will change the world; GlobalFoundries and Linear Dimensions collaborate on 14-channel programmable floating gate reference program
Semiconductor market revenue on track for 9.4 percent expansion; Graphene mystery solved; November 2014 semiconductor sales reach $29.7B; ON Semiconductor showcases new CMOS imaging sensor
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The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.
EUV will introduce unwanted patterning distortions that must be accurately modeled and corrected.
How to tame data file sizes, address fractured data files creation and streamline data review techniques.