Book-to-bill above parity in November; imec demonstrates graphene EAM on IEDM 2014; Amkor licenses copper pillar wafer bump tech to GLOBALFOUNDRIES; Desktop monitor market experiences growth
Podcasts Videos Webcasts Archive
Murata completes acquisition of Peregrine; North Carolina State University researches stacking semiconductor materials; SIA announces new president and CEO; Entegris announces availability of 450mm wafer carriers
Cypress and Spansion announce merger; SEMATECH announces promising EUV research; Global semiconductor sales reach $29.7B in October; Soitec and CEA-Leti establish new solar cell efficiency world record
Revenue from industrial semiconductors on the rise; Combo MEMS sensors market to reach $1.4B by 2019; Notebook PC market grows while tablets struggle; Book-to-bill below parity for two consecutive months
A new product scope for an expanded Information Technology Agreement announced; Silicon wafer shipments increased in third quarter; New CEO of SEMATECH; SIA board of directors announces new chairman
The growing sensors market; Texas Instruments to expand operations in China; GlobalFoundries partners in INVECAS; Worldwide sales of semiconductors hits record-breaking high
GLOBALFOUNDRIES to take over IBM’s commercial semi business; MegaChips acquires SiTime; imec and Coventor collaborate; Mergers and acquisitions shake up automotive semiconductor landscape
Pete Singer interviews new CEA-Leti CEO in Grenoble, France.
TSMC’s new low-power tech platform and ARM-based networking processor with finFET technology; New 3D IC being researched; Dow Corning offering new 150mm SiC wafers
EUV available at 10nm; Mentor Graphics appoints new VP of Embedded Systems; ProPlus expands operations in Europe; Rudolph releases new SONUS technology
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The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.
EUV will introduce unwanted patterning distortions that must be accurately modeled and corrected.
How to tame data file sizes, address fractured data files creation and streamline data review techniques.