SIA awards University Research Award; Fab equipment spending increase in 2014; Semi industry posts highest-ever January sales; 19th century physics could change future of nanotech, according to researchers at UC
Podcasts Videos Webcasts Archive
MIT research; Soraa’s most efficient LEDs; EU launches PLACYD; GlobalFoundries and Fraunhofer extend collaboration
Successful financing for Inpria Corp.; Record speed in silicon-germanium chip; MACOM acquires Nitronex; imec presents 79 GHz radar transmitter on 28nm CMOS
IBM looking for buyers for semiconductor business; Worldwide silicon revenues declined in 2013; SPTS opens Korean office; Leti launches PIEZOMAT
Entegris to acquire ATMI; New device from epitaxial graphene nanoribbons; Intel elects new corporate vice presidents; Reclaim wafer market growth
North Carolina State University’s new consortium for power electronics; Apple and Samsung remain top OEM spenders; SMIC announces 28nm readiness; Book-to-bill ratio continues to improve
Imec and Besi collaborate on thermocompression bonding for 3D-IC; AMOLED panel forecast; 3D graphene research; 2014 outlook discussed
Imec and AlixPartners to develop cost modeling solution; Semiconductor packaging materials market forecast; 2013 SEMI Award winners announced; Modest recovery for microprocessors
IC industry capacity leaders; Micron’s revenue surge; Xicato expands manufacturing facility; CES 2014
Hybrid memory development by AMD and Hynix; Intel’s 22nm mobile processor; Soitec and CEA-Leti renew partnership; IDT’s new president and CEO
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The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.
EUV will introduce unwanted patterning distortions that must be accurately modeled and corrected.
How to tame data file sizes, address fractured data files creation and streamline data review techniques.