IHS says Moore’s Law led to trillions added in global economy; Cadence and Applied Materials collaborate on CMP process optimization; Power transistors seen stabilizing and setting record sales in 2015; Nanowires could be the LEDs of the future
Podcasts Videos Webcasts Archive
Fab equipment growth continues in 2015; Fairchild launches first MEMS product, IC manufacturers close or repurpose 83 wafer fabs from 2009-2014; World’s thinnest light bulb made on graphene
SEMI updates World Fab Forecast; MEMS suppliers ride auto safety wave; Seven partners join CEA-Leti’s FD-SOI IC development program; TSMC on 10nm process node
First quarter semiconductor sales up 6% compared to last year; New study suggests that rapid innovation in semiconductors provides hope for better economic times ahead; Microchip and GlobalFoundries announce new 55nm embedded NVM; ASE and TDK announce plans for joint venture agreement
Applied Materials and Tokyo Electron terminate merger; Sensor competition, actuator recovery impact supplier ranking; Georgia Tech research offers novel cellular sensing platform for expanded use of semiconductor in biotech applications; Silicon Motion announces agreement to acquire Shannon Systems
Top 10 2015 semiconductor sales leaders forecast to include NXP/Freescale; Applied Materials announces new photomask etch system; North American semiconductor equipment industry posts March 2015 book-to-bill ratio of 1.10; Global semiconductor market achieves strong, broad-based growth in 2014
SEMI reports 2014 semiconductor photomask sales of $3.2B; Automotive touch panel revenues to hit $1.5B by 2018; Sensor shipments strengthen but falling prices cut sales growth; ClassOne enters ECD lab partnership with Shanghai Sinyang
SEMI reports 2014 global semiconductor materials sales of $44.3B; Cavendish Kinetics adopts STATS ChipPAC’s wafer level technology; MEMS shipments to reach 43.3B units by 2018; TSMC certifies Synopsys design tools for 16nm finFET plus production
NXP/Freescale merger to create an automotive semiconductor giant; Mentor Graphics releases new Xpedition Packaging Integrator flow; C3Nano and Kimoto Japan announce partnership; Brown University researchers develop new nanomaterials from silicon-based compound
Top 20 MEMS ranking revealed; Micron and Intel announce availability of their 3D NAND technology; GlobalFoundries and NXP Semiconductor develop a 40nm eNVM low-power process technology; SEMI releases book-to-bill report for February 2015
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The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.
EUV will introduce unwanted patterning distortions that must be accurately modeled and corrected.
How to tame data file sizes, address fractured data files creation and streamline data review techniques.