Time For FD-SOI?
Soitec COO Paul Boudre discusses what will be the best solution for 20nm – fully depleted silicon on insulator or bulk 3D transistors? The answer will likely include both.
"Sanjay, Different foundries have taken different positions on this. Some originally required the designer to tape out two..." - David Abercrombie

Deep Insights for Chip Builders
Soitec COO Paul Boudre discusses what will be the best solution for 20nm – fully depleted silicon on insulator or bulk 3D transistors? The answer will likely include both.
Just how easy is to move designs from one foundry to another? It depends who you ask.
What problems are we likely to face at future nodes and with 3D structures?
Just how real is 3D stacking and what are the main hurdles that need to be solved.
Michael Buehler-Garcia, director of Calibre Design Solutions marketing at Mentor Graphics, talks about the challenges in building 2.5D stacks and how testing them will become a major headache.
Bettina Weiss, who heads SEMI’s solar effort, talks about what’s new at Semicon and Intersolar North America, how far the industry has progressed and what stands in the way of widespread adoption of solar technology.
Jonathan Davis, executive vice president of SEMI, drills down into the state of the chip industry, what’s driving the changes and what the big issues are for manufacturing and design in the future.
Juan Rey, senior director of engineering for Mentor Graphics’ Design To Silicon Division, talks about 3D stacking and 3D structures on chips.
Karen Savala, president of SEMI Americas, looks at what’s new at Semicon this year, how the show is changing and what to look out for.