IBM scientists achieve storage memory breakthrough; Kateeva closes its Series E funding round with $88 million in new financing; Worldwide silicon wafer area shipments increased during the first quarter 2016 when compared to fourth quarter 2015 area shipments; New type of graphene-based transistor will increase the clock speed of processors
Podcasts Videos Webcasts Archive
Worldwide semiconductor capital spending projected to decline 2 percent in 2016; Worldwide sales of semiconductors reached twenty six point one billion for the month of March 2016; STATS ChipPAC ships over one billion fan-out wafer level packages; Rudolph Technologies appoints of Debbora Ahlgren as VP of global customer operations
Tim Lillie, General Manager, North America, provides a look at Presto Engineering’s operations in this corporate video.
Semiconductor fab equipment spending growth in 2015; NXP and Freescale complete merger; Atomically-flat tunnel transistor overcomes fundamental power challenge of electronics; Imec boosts performance of beyond-silicon devices
Researchers discover new phase of carbon; IDMs on track to outpace fabless semiconductor supplier growth; Advanced packaging to reach 44% of packaging services by 2020; European Commission approves Avago acquisition of Broadcom
ON Semiconductor to acquire Fairchild; CEA-Leti and partners announced three silicon photonics platforms; Micron unveils persistent memory technology; Wally Rhines of Mentor Graphics wins Phil Kaufman Award
New ams fab going to Marcy, NY: Startups and small electronics companies spent $78.3 billion on semiconductors in 2014; Pure-play foundry sales forecast to grow to all-time high in 4Q15; University of Colorado and SRC research accelerates microscopic imaging for next-generation nanoelectronics
Smart meter semiconductors on the rise; New research may enhance display & LED lighting technology; Demand for novel display materials set to surge in second half of 2015; SUSS MicroTec announces new competence-center for nanoimprint in North America
New research could enhance LEDs and displays; Intel to collaborate with Georgia Tech; imec extends its GaN R&D program; Strong silicon wafer area shipment growth reported in second quarter of 2015
Worldwide sales of semiconductors reach $84B in second quarter of 2015; Toshiba announces world’s first 16-die stacked NAND flash memory with TSV tech; Intel and Micron unveil 3D XPoint memory technology; Samsung cuts into Intel’s sales lead
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The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.
EUV will introduce unwanted patterning distortions that must be accurately modeled and corrected.
How to tame data file sizes, address fractured data files creation and streamline data review techniques.