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SMD: What does hybrid metrology accomplish in the process control flow?
Allgair: The structures are becoming so complex. You are trying to measure a particular application on a 3D device, where you have a lot of variations that already took place prior to the measurement step. Hybrid is one of the ways to address that challenge. For us, it enables us to use a lot of the information that is collected upstream for the measurement event you are actually doing. It allows us to understand, as much as we can, about the structure in terms of how it was processed and what it looks like prior to that measurement step. And then, for the variables you are trying to measure, it helps reduce some of the uncertainty of those variables you may not understand from that particular process step you are measuring. Again, that information can be thickness, compositional and CD.

SMD: Do you think directed self-assembly (DSA) will succeed? And does the industry have an inspection/metrology solution for DSA?
Allgair: As we keep driving litho, there is a decent chance that DSA will happen. We will probably try to postpone it as long as we can, and try and get through what we’re currently using. When it does happen, it may end up being a different type of solution than we thought. After SPIE, and looking at one of the papers from MIT, it looks like there might be a way to measure the structures that were used to pattern your DSA. It might be that we monitor that structure. Then, we will have some confidence that the DSA activity takes place and works. All told, if we can get a DSA system that works well, and there is a cost advantage to it, that could drive an earlier adoption for DSA. That is a big component to DSA.
Heidrich: We certainly see the promises. The cost reduction is there, but the challenges of proving low defectivity and performance still remain. Certainly, in the case of memory and related types of processes, where you have redundancy, DSA will get adopted earlier. There has been work on contact holes, where you can do reduction with DSA. When the yield is proven, and if the cost benefit is there, DSA will get adopted. But I think that is still quite a few years away.
Newcomb: DSA is just one of the options available. We have all been in the industry long enough to know there are multiple options. But DSA is the one you want to try to avoid as long as possible because there are many unique challenges. Will it happen? Maybe not. If it does, you have to put all of the pieces together to bring it into high volume production. The challenge comes down to defectivity and integration.
Shetty: DSA is exciting. DSA will most likely happen, but cost would be the biggest challenge in terms of making it production-worthy.

SMD: The industry is in need of new inspection/metrology breakthroughs and tools. Do you agree? And how does the industry fund the development of new tools when there are not enough R&D dollars?
Allgair: It is apparent that we have a need for some new techniques. The ones we’ve talked about are multi-beam e-beam inspection, CD-SAXS, helium ion and a higher resolution CD tool. These are addressing defect-inspection resolution, CD resolution, scatterometry and compositional analysis. The problem that we are trying to grasp is the people that use these new tools are the ones on the leading edge. Those are for devices at 14nm and beyond. There are not a lot of companies in that space. So, it’s not clear how many tools would get ordered at the leading edge. And the other problem is chipmakers like GlobalFoundries, Intel and others may not have provided a clear and concise message in terms of what our future tool needs are to the toolmakers. Regarding GlobalFoundries, as well as my peers at Intel, TSMC and others, we all need to get a little better organized in terms of defining our problem statement to the tool vendors. The second piece is how do you fund a new tool development program? That one is challenging. We’ve seen other funding models, where we have joined other companies and put money together to drive the development of a new tool in litho or to drive a consortium. It’s possible that chipmakers can get together and try to drive something along that line. Another possibility is that each customer could buy the first generation of new tools from vendors. That might be enough for suppliers, who can then seek funding on their own.
Heidrich: We see two things that are challenging from the R&D point of view. One is the rapid consolidation from our end-customer base. We have fewer than a dozen major customers left. In the near- or long-term, that number will likely get smaller. So you have to have fewer customers to absorb the R&D for all the products you need to develop. Secondly, we have very diverse and complex process flows that different customers are adopting. This could be a finFET flow, vertical memory flow, or a 3D device integration flow. So you have more demands on your R&D. Right now, we need to make sure the R&D dollars solve the hard problems and we leverage that learning across all the different end customers. What that means is that if someone has a unique challenge, it gets harder and harder to provide a custom solution.

SMD: What about VC-backed startups like Qcept?
Newcomb: If you go way back, the industry had lots of startups. You had tier-one customers of course, but you also had a plethora of tier-two and tier-three fabs in the world. Now, as an equipment maker, you are not going to get funding that easily, because there are maybe 12 or less major customers in the world. It also takes more money to develop products. The dynamics are also different. You have new memory and logic requirements. We are tying together the OSATs and fabs with 3D TSV integration. In addition, the industry is moving towards two major suppliers on the equipment side and a handful of customers on the device side. That dynamic makes it very difficult. The big challenge is how will the industry keep investing and address those types of needs?

SMD: What’s the solution to this problem?
Newcomb: In one possible solution, companies on the device side could pre-buy the technology rights to the first tool to help fund some of the required investment and R&D. Or maybe, we can better integrate the university work into a model that can be funded and driven into the industry to solve a problem.
Shetty: R&D is becoming expensive. The device nodes are shrinking quickly. And customers’ expectations are increasing. Across the industry, everyone is pushing to get a lower cost-of-ownership and higher productivity. That’s just a fact of life. There are maybe 12 customers out there. But between the joint ventures and consortia, there are maybe four or five R&D centers out there. Today, it is very important that you are involved with these R&D fabs very early in the process. Then, the tool evolves with the process. So when customers move into production, the tool is already mature and ready to go. On the other hand, the devices are changing so much. And in a lot of cases, the customers themselves don’t know what’s going to happen.

SMD: What about finFETs?
Newcomb: 3D structures like finFETs not only require more metrology and inspection steps, but they involve a lot more complexity. You are not just looking at the information in the x, y, and z axis, but also at the atomic level of x, y and z. You are asking things like how does that device come together? What is the structure of that device? Does it meet the specs? We are starting to see some interesting interactions with existing process tools types, whether they are across the edge or wet cleaning. When you use existing technologies, and try to build 3D structures, you are getting defect signatures that we’ve never seen before from net Vdd perspective. You also have all of these defectivity models coming forward and you have to deal with them.
Allgair: Going to 3D has created numerous challenges for us. We see tenfold measurement problems as we go to 3D. A lot of things you see in 2D tend to get amplified as we go to these 3D structures. In an x, y and z matrix, you need to ask: ‘The atoms are there, but are they the ones you want? Are they electrically active or not?’ We are trying to use the same tooling that we currently have available. You will see the CD-SEM, OCD, and the overlay tools you are familiar with. With finFETs, we can do some things, such as CD, height, profile, spacer, and thickness. Some of these applications can be done using scatterometry or CD-SEM or a combination of that data set. Then, we see some real challenges when it comes to compositional analysis. In finFET devices, we’ve got compositional measurements like SiGe with a percentage of germanium and a percentage of boron on a 3D structure. That’s a very complex measurement. Finally, we try and do measurements on test structures. The test structures don’t always mimic what’s actually taking place on your device. That really adds to the complexity of trying to manufacture finFETs in a stable manner.

SMD: What are some of the issues with stacked 2.5D and 3D devices?
Newcomb: As we turn to the 3D packaging world, and we think about stacked memory or memory on logic, we have techniques like traditional optical inspection. Although it will be important for 3D packaging and 3D ICs, you have to be concerned about a whole new class of things like sub-monolayer metallic contamination within the device area. If these wafers need to be thin, and I need to expose the TSVs, I start seeing copper defectivity and sub-monolayer issues. Now, I am trying to stack multiple known-good die. As we package these known-good die in 3D structures, and if you have one mistake like sub-monolayer copper residue, that will make multiple known-good die no longer any good.
Heidrich: Plus, you hand off a known good wafer to someone and then you need to integrate it. In effect, you are doing double metrology and double inspection. And then in the process itself, there is a lot of complexity we address in terms of TSVs. Metrology and inspection for that whole flow must be addressed for cost, performance and reliability.
Allgair: If I look at the 3D TSV side, the idea of stacking structures has created a need for new tools. We have been looking at new techniques, which should work out reasonably well. We are making pretty good progress.

SMD: What are the big challenges in metrology and inspection?
Allgair: As we keep scaling our devices and improved the resolutions, there is a need to not have much interaction with the measurement technique and the sample we are measuring. The information we want to get is also becoming more complex. So in the past, we had one-dimensional CD types of measurements. Now, we really want to understand both 2D and 3D information for the structures that we are measuring. We also have a desire to look at how the structure looks, versus what the design intent was. Of course, the structures are becoming more and more complex to measure. When we look at finFETs, we want to measure everything that we typically would have measured on a normal 2D CMOS device. Except now, we are trying to measure all of these parameters in 3D. That’s becoming very complex now.
Heidrich: Resolution, sample interaction, and complexity drive us, as well as 3D requirements. Top-down measurements, and how wide something is, are important now. How tall is the structure and the undercut are important, as well. The idea of measuring more parameters on a given sample is driving our tool technology and software. But also important, the users of the tools have to deal with even more information, whether how they deal with it for process control or how they collect it from a metrologist point of view. In addition, there are a lot of new architectures coming up in several different areas and all at the same time. One of our challenges is to come up with comprehensive solutions for finFET metrology and 3D ICs for stacking.
Newcomb: The defects continue to get smaller and smaller. But the complexity of those defect issues is being driven by a proliferation of new materials throughout the process at the front-end-of-the-line and the back-end-of-the-line. So when you combine the materials, the device structures and the process technology, we have the continuing challenge of physical defect inspection. But now, we are finding more and more non-visual defects becoming a major part of the yield-critical defects in the fab. Being able to detect those non-visual defects is becoming important, especially at the advanced process nodes.
Shetty: We all agree that resolution is the biggest issue out there. As these device sizes shrink, they are behaving very differently. The information you are getting from these inspection tools is not correlating. Customers are also seeing big yield issues, mainly at the edges of the wafer. And a lot of these inspection and metrology tools are limited on the edge of devices. On the device side, there are two big challenges. The devices are going in vertical dimensions with 3D structures, such as finFETs. On the horizontal direction, customers are going from 300mm to 450mm wafers. This changes the dimensions both in the vertical and horizontal direction, offering more and more challenges in terms of stress, overlay, lithography and CD. We are also bringing in high-stress films like high-k, silicon germanium and thin films. The challenge is can the current inspection and metrology tools keep up with all of these changes taking place.

SMD: Are the existing metrology tools keeping up or do we need new breakthroughs?
Allgair: If you look at the tools available right now, we are primarily controlling the line with the things everyone is used to. We have the CD-SEM, scatterometry, and we have the typical overlay techniques. We use a little AFM. In terms of inspection, we have brightfield inspection and some e-beam inspection. When we look across that tool set, we do see the need for improvements as we move to smaller device dimensions. On the imaging side, we need increased resolution in order to measure some of these features. We are seeing improvements in the CD-SEM. It might be able to get us where we want to go. There may be a need to have a higher resolution-capable tool. We would like that tool not to damage the feature if at all possible. On the scatterometry side, we think that technique is pretty extendable. We start to run into issues with some of the materials interactions. Then, we question the extensibility. There is some work now that says it may extend to the 9nm node before it starts to lose some steam. We have looked at perhaps using another technique like X-ray to extend it.
Heidrich: For the most part, we are doing two things. We are taking tools like our OCD tool and continuously improving the signal to noise for a given configuration. We are also adding more data channels to the tool. We are pretty confident following those approaches we will continue to extend down to many future nodes, and well below normal diffraction limits.

SMD: What about inspection and overlay?
Allgair: On the inspection side, brightfield has some steam left, but it has become very challenged. The idea of having e-beam inspection helps solve some of the resolution problems. But we have a throughput challenge there. So then, we have the concept of multi-column, e-beam inspection. If we could make it work, and have the throughputs that we want, that’s attractive to us. If I talk about overlay, the idea of measuring overlay right off the device structure could be very useful.
Newcomb: We think non-visual defect inspection is the next big thing on the horizon. Most of these leading-edge fabs will say that up to 30% of their yield problems have a ‘no defect found’ category. That basically says I know I have a defect issue at the end of the line and I can see that in my yield maps, but I have no corresponding or matching inspection data from the process line from all of these optical inspection tools or e-beam. Existing tools can address 70% of my defect problems. But I still have 30% of my yields, in which I don’t have a good method to attack from an inspection and yield engineering perspective. That’s where non-visual defect inspection can play a major role.
Shetty: Traditional tools from KLA and ASML do a good job of measuring the targets as a measurement itself. While they do a good job bringing information to the scanners, we are focusing on a tool that gives you non-destructive, high-resolution on the edge of the wafer. And it mainly tells you information on the stress, the shape and distortion. The technology we offer does not replace the traditional overlay tools from KLA and ASML. It’s actually a complementary technology.

SMD: What other breakthroughs are needed?
Heidrich: We see a growing demand for in-line, on-device compositional metrology. That’s an underserved market right now. There are very few tools that have the spot size, resolution and the discrimination that satisfy customers out there.
Allgair: We have been pushing the idea of hybrid metrology, which is the idea of using data from previous process steps. So now, your downstream measurement tool has at least some information coming in about the wafer to make your measurements a little bit more accurate. This is one of the things that could help solve this overall problem of trying to determine what the feature looks like in 3D. From a user perspective, I would like to have a complete picture of what it is I am measuring in the 3D space. I want to know where every avenue is. I want to know where it is located in the matrix, what type it is, and what the electron activity is. That’s ultimately what we want to know. We are still a long way from that. That seems to be kind of the new Holy Grail, so to speak, of metrology.

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SMD: How far are we from having the models we need to enable 3D ICs? Are we going to get them from the foundries?
Smith: You do inevitably have to get basic models from the manufacturer or whoever is supplying the source of the materials even. We’ve talked about models of manufacturing materials—chemicals even. There are models for everything. But certainly the consumer that we’re talking about in this room is a semiconductor design engineer or a packaging engineer so they’re going to need to know what rules they need to follow to get their device manufactured within enough reliability, performance, longevity and cost in order that I’m going to be able to take responsibility on behalf of my company or my employer. It goes back to the first question of who is responsible. It’s the guy who is writing a check, but there’s trust. And that trust is done through a formal contract, a set of models. The models come from the engineering work that the supplier has done and the work that they do is often done based on work that their equipment manufacturers did alongside research organizations and universities around the world.
Jerraya: In fact what you have today you have many of the pieces. The work today is to put these pieces together and make it simpler, more automated. Process related modeling is almost there. We know all of these have been done for some cases, for some technologies; now the point is how to make this all automated and inserted in the tools, all the backend tools, all the modeling simulation, all the physical simulation, the power, thermal, mechanical simulation—all those things we need. The pieces are there.
Smith: We were talking about collaboration earlier. I see a lot more now even within our customer base that the semiconductor design companies historically have had separate departments responsible for each of these pieces: a packaging department, an IC department, a CAD or EDA department, IP modeling department, and more. For the first time I’m starting to see them have meetings with their vendors together, which hasn’t happened in my experience. I’ve been in EDA for over 30 years and I haven’t seen that before so I think they’re forced to talk more closely to one another inside the organization because the challenges are coming from the combination of the package, the interaction with the ICs, the stacking, the foundries and the vendors. It’s happening naturally.
Kaiser: Something also that is encouraging from my viewpoint is that the possible targeted systems with 3D have been clarified, and that’s very encouraging. Now we can clearly see different products that can be targeted with 3D and that’s very encouraging because it gives the objectives to reach. And as an EDA provider this really gives the direction to follow. Now with 3D we can really see that some products, maybe memory cubes, there are the interposers, there are the memories on digital logic—these are very clear targets. This really gives the path towards the tools development and collaboration.

SMD: What is the biggest weakness other than the integration piece that we talked about?
Smith: It’s not any weakness. I think it’s more just balancing in the force of business. It only becomes unbalanced if technology is no longer able to deliver reliably the next generation. Everybody’s been predicting Moore’s Law is going to die. Well, it’s still going on, and we’re talking about 14nm. With packaging, they’ve been talking about wire bonding eventually giving out or memory design. We’re still dealing with DDR and low-power DDR, DDR2 and DDR3. Each one of those extends the lifecycle of a certain technology so the question is, at what point does it become imbalanced for a particular company who has a need to fill? When that happens they have to fill the void with the next jump, and in this case it will be 3D or 2.5D. It’s always the same question. It’s not a matter of if, but when. The technology is there. I think we are starting to see signs now of life with a certain set of classes of application. We’ve already seen memory design done in stacks so we know that that can be done. We have also seen 2.5 D being done with a number of companies like Altera, Xilinx, TSMC, and the next one seems to be showing signs of life right now so if we are lucky we might see next year at DAC an actual physical example. I know we’ve said that for many years, but it actually as long as the imbalance stays there it’s going to get filled with a real device very soon I think.
Jerraya: 3D has been around for long time, and there has been a lot of hype around it. Today we see the light in the tunnel. Coming back to the question of the strength and the weakness, it relies on the business part because there are two kinds of forces. Some people are willing to control this 3D and take the benefits, and some people are scared of it because it’s going to change business. In fact, what we are near to making, which is 2.5D, will create a change in the PCB business in system integration. It changes in terms of the packaging part but also the procurement of chips, because we are going to buy chips at advanced nodes provided by some design houses or whatever they are, and we will then package them into a system. This is new, and it is a step further in integration.
Smith: Even though we’ve been doing this for years we could be completely thrown off by some random element. We will look at our other favorite topic: smart phones. Who would have thought five or six years ago the phone companies could have a game changer? It wasn’t even new. It was existing technology. But somebody with the right idea and the integration skills that made it happen. The same will be true here.

Part one of this series can be viewed here. Part two is here.

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SMD: What is the general state of the next-generation lithography (NGL) arena?
Fujimura: I have been in the industry for a long, long time. There have not been this many alternatives that have a chance for success. It’s definitely an interesting time.

SMD: But EUV is clearly late. Does the industry need to allocate more R&D dollars to the various NGL technologies beyond EUV?
Fujimura: Yes. There should be more investment in all areas. Unfortunately, semiconductors in general are not really a fit for a pure venture capital model. It’s too expensive and the returns on any individual bet are not high enough. So it has to be the larger companies that step up and create a fund, or maybe even some kind of joint fund. That’s probably not going to happen. The larger companies may need to collaborate somehow, probably quietly, and voting with their dollars. Don’t just vote on the top one. Vote on several alternatives.
Rey: I agree. I am absolutely convinced that more money is required, because the challenges are bigger. In fact, the need for increased functionality is everywhere. The standard way of actually getting that increased functionality is really becoming a lot more difficult by following the standard path. It is a lot more difficult to do patterning today. There is also a transition toward finFETs, SOI, fully depleted SOI or some other technique. There are other things that are required at the transistor level. It is getting more difficult everywhere.

SMD: What other challenges do you see?
Rey: For example, in the data communications path, there is a need for transmitting more data with lower power and cost. I mentioned silicon photonics because it is a technique that seems to offer the potential for much larger bandwidth for the same amount of power as copper at shorter distances. But no one knows how do to it at a cost that is feasible at this moment. The industry is starting to respond in a very interesting direction. Interestingly enough, the silicon photonics conferences were once attended exclusively by physicists. Now you have keynote presenters from companies like Facebook and Google. So you can see that the large companies that have needs in that direction are paying attention to what’s happening with the technology. The industry as a whole requires more investment from the companies that are getting the benefits of having a path towards more functionality per unit area. Hopefully, they will follow with the funding that is required to bring some of these technologies forward. The industry at a higher level needs to get involved with the technology to enable what customers want.
Fujimura: And let’s take cell phones. For the most part, they still don’t work. You can’t rely on the cell phone to give you a reliable connection. There is a lot more that can be done. We need a lot more and better technology.

SMD: Let’s get back to lithography and EUV. When will EUV finally move into production?
Enami: At the 14nm node in 2016.

SMD: What does Gigaphoton’s EUV source roadmap look like?
Enami: The industry target is to have a 50-watt source in 2015 or so. This is because 2016 is the target for the mass production of DRAMs with EUV. Our milestone, of course, is to reach 50 watts. Our current source is operating at around a few watts. Within this year, we want to achieve 20 watts. In Q1 of next year, we need to reach 50 watts. And if possible, at the end of next year, we want to reach 100 watts. A 100-watt source can produce around 60 to 70 wafers per hour. If we can reach 100 watts by the end of next year, we can provide a source to the customer by 2014 or 2015.

SMD: What’s going on with laser light sources for traditional 193nm lithography?
Enami: We are doing both EUV and deep UV sources. Of course, the laser for DUV is working at the 60-watt level today. That translates to 175 wafers per hour. The recent ASML scanner hopes to reach 200 wafers an hour. That requires 90 watts of power. The actual multi-patterning scanner requires 120 watts in one or two years. We are also developing 120-watt lasers. We’ve almost achieved that target. In production, a 120-watt source power can be applied for 450mm scanners. For deep UV laser sources, multi-patterning requires more R&D dollars. Customer requirements are very tough. Even for DUV lasers, they want cheaper, more durable and higher-availability technologies.

SMD: Do you see other challenges with EUV beyond the source?
Fujimura: EUV needs very accurate masks. If the mask is not accurate, it will show up on the wafer.
Rey: Defects on EUV mask blanks can’t be completely eliminated. That is extremely disruptive. Given that this is the case, what can be done at any part of the design flow to compensate for that? It is possible to find solutions for it. But it is not easy to determine today if there are going to be practical approaches to that. Essentially, you need to know something about the design to be able to use a mask. In this case, you don’t know where the defects are, but you still need to use the mask for that design. That is not something any manager in the food chain wants to deal with. People are starting to scratch their heads about this issue, but nobody seems to be too willing to embrace it. It will be interesting to see how Intel, IBM and TSMC are going to deal with it.

SMD: Will DSA make it into chip production?
Fujimura: I say positively yes.
Rey: I have a positive feeling about DSA. So far, the whole infrastructure that exists today for doing the creation of the shapes for the actual mask seems to be similar. But with DSA, it seems like new models need to be adapted. They need to be proven that they can work in terms of memory consumption, speed and scalability at full-chip level. If you look at it, all of the techniques applied today are essentially based on the resolution limits of photolithography. In the beginning, it was possible to print something very close that was drawn. With the exception of source-mask optimization, pretty much everything follows that key concept. For example, you want to print a rectangle. You start with a rectangle and you see how much you need to modify it. When you apply the model, it predicts how the rectangle is going to be printed. The modifications we’ve seen in DSA are much larger than that.

SMD: Can EUV play a role to help DSA?
Enami: DSA does require guide patterns. To make the guide patterns, you need traditional lithography or EUV.

SMD: If all else fails, the industry can move to multiple patterning. Are EDA tools ready for multiple patterning?
Rey: The tools can be extended. If we go from double patterning to triple patterning, the complexity is a lot larger. But the expectation is that hopefully you won’t need triple patterning everywhere. The algorithms are too complex. There are flow approaches to make the tools feasible. From a conceptual point of view, they are well understood. But not all the tools at full-chip level are completely ready. They are in the process of being developed.

SMD: Let’s re-visit e-beam again. Why is direct-write and maskless so critical for the industry?
Fujimura: Hopefully, people see the benefits. It’s generally not for huge volumes. Let’s say you want to develop a chip and you are not sure it’s going into high volume production yet. It’s getting incredibly difficult to do that now. Innovation in the ecosystem supply chain is being stifled because of cost issues. To help those types of customers, we can do something like direct-write, where there is no mask cost and there are lower volumes. These are important things for the ecosystem to invest in for the sake of the whole semiconductor industry. We are trying to do that with our eBeam Initiative. We were talking about 450mm earlier. With any new technology, in order to get the level of funding you want, you have to appeal to the mass market. But some investments are better for the long term. E-beam investments can be very important not just for the e-beam community, but also the entire semiconductor supply chain.

SMD: How does maskless gain traction?
Fujimura: We also see it in complementary lithography. In complementary litho, you can draw the lines with nanoimprint, EUV or anything else. And then you cut the lines using e-beam. I think that kind of concept being prompted by the major players will be a great way to fund and kick-start the technology into the mass market.
Rey: We have been looking at e-beam direct-write techniques. But we completely agree with Aki about the level of investments in maskless. We have looked at the published information in terms of how much research money has been going in EUV as compared to direct-write. There are orders of magnitude difference between the two of them. In terms of the type of research that we are doing, Mentor has been following the Imagine program with Leti in Europe for direct-write. We see a level of maturity that is still required to even understand the whole magnitude of what the problem is. We don’t have clarity, as compared to what we have for multi-patterning techniques. There is a large gap between the two things.

SMD: When will maskless lithography go into production?
Fujimura: There are people that use direct-write for the 65nm node. But predicting the future has its risks. So that’s a difficult question. It depends on the volumes. In some ways, it’s ready to go.

SMD: Any thoughts on nanoimprint?
Fujimura: One of the things about nanoimprint is that it enables line and space patterns. It seems like they are having some success in being able to print small features very reliably. It’s great for that. It’s also perfect for the complementary lithography idea. Nanoimprint can draw lines. And then e-beam can cut the holes. Something like that can be a good combination. One thing to note is that nanoimprint masters are made with e-beam technology. It’s 1x dimensions, unlike photomask, which are 4x dimensions. It’s basically a direct-write problem to write those masks.
Enami: Nanoimprint is very effective for NAND flash applications. One manufacturer has started pre-production at 11nm by using nanoimprint.
Rey: We are having conversations regarding what is required at 10nm these days. They all seem to be coming from the other techniques and not from nanoimprint.

SMD: DFM is playing a greater role in lithography and in the manufacturing space, right?
Rey: There is something interesting happening. There is increased communications between the manufacturing community and the design community. Many of the barriers have been overcome. This includes discussions to make the process more efficient. And so at least today, the industry is more aware and open to have a dialogue. Many years ago, to get the two sides together was impossible, because everyone was pre-occupied with one’s own worries. They refused to have a discussion. Right now, a dialogue is expected.

SMD: What DFM is needed in litho and other parts of the flow?
Rey: Right now, you see it in double patterning. You see it in the establishment of rules that bring more regularity in design. You see it with several types of things that extend traditional design rule checking. For example, you establish pattern matching techniques that essentially identify the patterns you can manufacture. You can use the information in a way that designs are efficiently done. Each one of these techniques brings all sorts of limitations and needs. But there is a willingness to bring the design and manufacturing communities to the table to discuss them.
Fujimura: Designers want more flexibility. For example, it seems like you should be able to use the techniques like what Tela Innovations is talking about and apply them to SOC designs.

SMD: It’s a cliché, but isn’t there more collaboration in the industry now?
Fujimura: That’s a trend. The whole ecosystem is collaborating together. Even competitors are working together, because the problem is so hard. Making sure the pie continues to grow is the number one issue. But it’s a tough shift. You start with competition. The mindset is if you tell your competitor what you’re doing, then it’s not going to work. But if you don’t talk to other people, then you can’t start the collaboration. If you don’t sell the idea that you have, and try to promote it in a public forum, you can’t make it go. You almost need your competitors to line up with what you are trying to do. That way the industry is working on one thing and investing enough in that. And that way it can actually happen on time.
Rey: A few years back, (IBM fellow) Bernie Meyerson made the point at a keynote at SPIE, where he showed the need for collaboration across the board. This included the process side for developing next-generation technologies, as well as the design side. There must be interaction between the two communities. And at that point, Intel was not that open. But clearly, the industry is moving in the right direction.
Enami: Collaboration is everything. Otherwise, nothing happens.