At 130nm, the introduction of copper interconnects, 300mm wafers and low-k dielectrics left the entire supply chain breathless. There had never been as many changes at a single process node in the history of semiconductors.
At 28nm, the number of changes will pale compared to what’s necessary at 20nm, and that will pale to what’s required at 14nm. But unlike 130nm, when most of those changes carried over into future nodes, the add-ons for each additional node will dwarf the changes at the previous one. In the future, each new node carries a bucket of new challenges, approaches, tools and methodologies.
Even technologies that supposedly are well researched haven’t been solved in volume. Double patterning is well understood, but it’s still not ready for mass adoption. Even high-k metal gate technology hasn’t achieved widespread adoption at 28nm.
Interconnects will become more difficult as RC increases with smaller wires. Triple and quadruple patterning might be required even with the advent of EUV—assuming EUV materializes in the first place. And DSA may be used in conjunction with any patterning or assembly in the future.
All of this will provided added impetus for stacking die. While some technologies will need to stay on the Moore’s Law road map—think high-performance processors and memory, for example—others will not. Analog, IP, and even specialized functions such as MEMS can be done at older nodes ranging from 65nm to as large as 0.5 microns, and still be packaged with 14nm logic and memory.
What will be interesting to watch, once that happens, is just how the supply chain breaks apart and reassembles as technologies are manufactured in nodes that are appropriate for their application. So far we are just thinking about the changes. Once they occur, there may be as much focus on 200mm fabs as on 450mm wafer production. And the list of things to worry about will certainly be entirely different than with everything being created on the same die for the latest process technology.