Bigger Shifts Ahead
By Ed Sperling
At 130nm the manufacturing portion of the semiconductor industry struggled with copper interconnects, 300mm wafers and immersion lithography. At 20nm and 14nm it will have to grapple with double, triple and possibly even quadruple patterning, new gate structures, the usual increases in process variation, far more expensive designs, complex challenges in attaining reasonable yields and in connecting those designs with the manufacturing side, and new stresses and problems caused by through-silicon vias.
It’s no wonder that many of the large chipmakers are looking for tools that can create 450mm wafers. With costs expected to skyrocket and the breakeven point for creating chips expected to rise significantly, anything that can be done to offset these rising costs—more dies per wafer, for example—will be extremely welcome.
Under the covers, though, there is an even more fundamental change underway, and it’s an amalgamation of all of these issues. The next couple of nodes will be the real cross-over for business driving technology at every step of the supply chain. While some parts of the supply chain already have felt the heavy hand of business first, for the most part the semiconductor industry has been all about technology first and business second. That’s about to change.
This doesn’t mean that progress halts, of course. The progression of Moore’s Law to several nodes beyond 14nm is assured, even though the exact single digits of nanometers seem to be in flux. The show will go on—but differently.
For one thing, it’s likely that not all parts of even the most advanced chips will be manufactured at those nodes. The progression toward stacked die is a recognition of these business issues first, mixing and matching subsystems that are manufactured and proven at different process nodes because of cost and time-to-market reasons.
So is the move by companies such as Intel and Samsung to adopt a foundry model to offset the rising costs of equipping state-of-the-art fabs. And so is the more widespread adoption of system-level design and design-for-manufacturing, which is propelling the big EDA companies to invest further in design for test, manufacturing and yield tools.
Lurking in the background of all of this is DSA, which may yet prove to be commercially viable beyond 14nm, although it’s uncertain just how that will affect the cost structure in a commercialized operation where consistency and quality are guaranteed. DSA is an interesting prospect, but whether it can interrupt decades of an almost linear progression remain to be seen.
But one thing that will change is that numbers are now the most important—time to first silicon, time to sufficient yield, time to profitability, the cost of getting to all of these steps and the crossover point for return on investment. The technology used in each of these steps will become less important as each node progresses and the challenges and risks continue to mount, unless it also has an associated way of reducing costs even further.
As an industry we have created technology that was considered science fiction just a decade ago. Going forward, we will have to figure out a way to keep adding more value for a similar cost—and that challenge will touch every company and person involved in this industry, as well as others in related industries such as software and services.