At 22/20/16/14nm the semiconductor industry is experiencing a rather new twist on Moore’s Law. Smaller, as in smaller feature sizes, is no longer assumed to be cheaper—or at least not for everyone. In fact, the cost per transistor for the first time in more than half a century could rise in some cases.

Whether this outlook improves as the semiconductor industry gains more experience with finFETs and the newest processes remains to be seen. There will be some economic efficiencies, for sure, but the best guess is they won’t be as large as in the past due to double patterning, more complex design costs, and a variety of other physical and electrical effects.

There were indications of problems ahead back at 90nm, when classical scaling ended. At each new process node before that, a feature shrink was associated with a doubling in performance and a reduction in power. After 90nm, the numbers started dwindling.

But that was only the advance guard. At 20nm, with double patterning, and more recently the introduction of finFETs, the number of design issues that have to be resolved and verified is exploding. It takes more man-hours to produce a chip, more tools, more metal layers, more mask sets, more re-spins, more time—and more money. In fact, it takes lots more money, from the design all the way through to the fab equipment used to make the chips. And even then, the level of confidence that designs will work is going down as complexity goes up.

The solution being floated around now is to build a bigger wafer. If you can increase the size of the wafer, then you can amortize the cost of double, triple and quadruple patterning over the entire wafer, which in turn evens out because the number of dies increase. That works fine mathematically, and mathematicians will remind us any chance they get that math is the only pure science.

Engineering is a science, as well, but it doesn’t rely on pure formulas. It’s a collection of incremental advances and systematic approaches to problem solving, and when you have 2 billion transistors on an SoC—and multiple power islands and voltages, clock domain crossing issues, electromigration, electromagnetic interference, thermal interference, memory contention, layout issues and insufficiently characterized IP—there is a huge challenge to verify that it all works. The functional and physical components of a chip need to be understood and digested by engineers working under extremely tight deadlines with software that may or may not work properly out of the chute.

Add to that uncertainties about yield, test, and random process variation at very deep (as in future single-digit) submicron geometries, new stress effects and mask issues with double, triple and quadruple patterning. Suddenly, what looks look a simple math formula isn’t so simple anymore. In fact, it’s not even a mathematical formula. It’s a risk/reward model based upon some very uncertain assumptions and some very real risks.

For companies such as Intel and Nvidia and some of the memory makers, this can be controlled with very regular layouts. For companies such as IBM and Apple, it can be absorbed by the end-device cost. But for SoC makers, particularly those racing for a socket with complex design, the risk of pushing to the latest node is high enough. To use a 450mm wafer may or may not improve that equation.

The ROI of moving forward with 450mm wafers will continue to be scrutinized, particularly on the most advanced process nodes. There are some very smart people working on this problem, and they often come up with solutions no one anticipates at the outset. But this is hardly a straightforward formula anymore, and no matter how clean the math may look or how linear the path may seem, reality still could turn out to be much different.

—Ed Sperling

There always will be a few big companies marching to the latest process node available to them. The problem these days isn’t their commitment to pushing forward. It’s the baggage train following them. It’s getting longer, more diverse, and in some cases, it’s falling out of sync.

The foundries are out in front with 14nm finFETs, and they’re already working on 10nm transistors—possibly with a 14nm process on the back end. They have taped out test chips, have working prototypes, and they’ve got many of the kinks worked out.

The problem is that while some of the EDA tool chain has been working side by side, the entire tool chain has not. And even though the big EDA companies have been pitching end-to-end solutions, chipmakers don’t want to get locked into any single vendor’s flow.

Consider the recent ruckus over dueling power formats for verifying chips. Two standards would have been a non-issue if chipmakers had opted for one vendor’s tools. Instead, they pick a combination of point tools and best-in-class pieces out of multiple vendors’ flows, then cobble them together into their own customized version. The result was a half-dozen years of complaints, delays and hair-pulling, which only now is beginning to subside.

That’s only one piece of the puzzle, too. Lithography is in flux, which means we may soon witness the advent of triple or quadruple patterning. The departure of ASML CEO Eric Meurice and the ascension of CFO Peter Wennink to the top post doesn’t bode well for getting EUV out the door anytime soon. Whether there is a suitable replacement for EUV remains a matter of speculation. If the industry opts for directed self-assembly as a replacement strategy, the entire EDA industry will have to revamp its tools.

And the supply chain still isn’t prepared for 3D-ICs, even though many of the technologies necessary to make this possible appear to be ready. The issues of liability from two known good die producing a bad chip remain unsolved, so at least for the next couple of years this technology will see only limited use. Stacked die using an interposer layer will likely progress faster, but how much faster remains to be seen.

Nor is this issue strictly confined to fabless companies. IDMs and fabless companies are both facing the same hurdles. We are at a point where the big equipment makers and developers of the processes have made great advancements, but the rest of the supply chain necessary to churn out semiconductors will take years to fully catch up. This is difficult stuff, to be sure, and not everything moves at the same pace. But in this case, we may be reaching the point where everything will begin to move more slowly, and the various pieces are so complex and so expensive that no one—not even Intel, IBM or Samsung—can afford to progress any faster than the supply chain allows.

What an odd way to level the playing field.

—Ed Sperling

Linear progressions have a hypnotic effect on even the smartest people. They lull everyone into thinking that progress—or at least a progression—is a straight line, with little or no recognition that things are changing around the edges.

The periphery is definitely changing, though. And over the next couple of process nodes, the semiconductor manufacturing industry either will have to figure out a strategy for reducing the cost of manufacturing semiconductors, or it will have to start working in a different direction altogether.

There are several factors at work here:

1. Lithography. This is by far the best-known and understood roadblock to progress. After billions of dollars of investment and years of delays, EUV still isn’t ready. For anyone familiar with this technology, that’s not particularly surprising. This is hard stuff to get right. The big problem is the power supply, but there are scattering and sidewall issues that are so difficult to solve they make your brain hurt. It may never be fully solvable, which is why so much attention has turned to directed self-assembly in recent months. DSA has its own pitfalls, though, and it remains to be seen whether it can ever truly replace 193nm immersion.

2. Metrology. So far there is no viable replacement for CD-SEM, which is to metrology what 193nm immersion is to lithography. Beyond 20nm, it’s harder to get a clear image to take accurate measurements. What comes next is a matter of debate, because while solutions do exist they also are destructive to the features they’re measuring. In a world defined increasingly by the low double digits of the nanometric scale, this is a big problem.

3. Design and DFM. The cost of designing complex systems on chip is going up significantly, which is part of the reason companies such as STMicroelectronics and Broadcom are making the most of the 28nm node. There are no finFETs yet, no double patterning, and there is the option now used by ST of fully depleted silicon on insulator with body biasing. Moving forward requires a big jump in complexity, time, and much more restrictive design rules, and even then yield is something no one is talking about yet. And with chipmakers now responsible for the wafer instead of just known good die, that’s a big leap of faith required. Add in 450mm wafers and the risk and cost may go significantly higher without any guaranteed returns.

One alternative, which will likely unfold in several steps, is through innovative packaging. In some respects, this is a sharp left turn from the feature shrinking, but ultimately it could be complementary. The big hurdle in 2.5D stacking has been the cost of the interposer, but given the rising cost of designing, manufacturing and characterizing chips at advanced nodes, this may pale in comparison. Full 3D stacking still has some issues to work out, notably around the TSVs.

What also will likely unfold, once stacking becomes more mainstream, is an ecosystem of IP—probably fully integrated subsystems and platforms developed as full die produced at whatever process node makes the most sense. For memory and logic, this is likely to be at leading-edge nodes. For analog and mixed signal IP, it likely will be at older nodes. And for I/O IP, it likely will vary depending upon whether it is a new standard or legacy.

Progress is hardly at a standstill, no matter what happens. If EUV miraculously appears on the horizon with a power supply, the path forward may indeed be linear for another couple of process nodes. But even then, there are challenges.

What’s encouraging, though, is that progress won’t stop no matter what happens. It will be less linear, but you don’t always take a straight path to reach a better solution.

—Ed Sperling

FD-SOI at 28nm, or finFETs at 20/14nm? To companies looking at the cost equation, the total market opportunity for SoCs and the NRE required to get there, this is still a manageable formula. It requires lots of number crunching and some unknowns, but by the time you get done with the math it still falls within an acceptable margin of error and the choices are relatively simple.

For foundries, the makers of EDA tools, and even IP vendors, there is no such accepted distribution to fall back on. For one thing, many decisions have to be made well in advance of the market. If there is no process at 14nm, there are no 14nm chips.

Good forecasting has always been critical to the foundry model, but it is becoming critical to the entire ecosystem. What happens, for example, when delivery schedules of key pieces go astray? EUV was supposed to have been ready several process nodes ago, and it still isn’t ready—despite billions of dollars of research and the best minds in process technology and physics trying to get the power source to the point of commercial viability. How do you plan for that? Answer: You can’t.

And how do you plan for eletromigration causing bigger problems than anyone expected, or a shortage of some key materials caused by geopolitical crises? How do you know black-box IP will work as planned next to other black-box IP? And even worse, how do you plan for your competitors leapfrogging you because you didn’t think the technology was worth investing in, or at least investing on a certain timetable?

FD-SOI is a case in point. Will there be enough big customers to warrant the investment made by the Common Platform companies? At this point the answer appears to be yes, but can companies like TSMC and UMC squeak by focusing on finFETs instead? Or will they ultimately need both finFETs and EUV? And by that time, where will stacked die be?

Timing is everything in business, but at 14nm and 10nm a timing error could cost tens of billions of dollars. It’s turned into a high-stakes poker game, where everyone is all-in all the time. What’s different this time, though, is that going all-in requires a commitment by the entire ecosystem, from DFM, DFT, DFY tools vendors to substrate suppliers, packaging houses and foundries. This is a team effort, but every member of the team has to excel for it to work. And given the growing list of challenges, timing will be much harder to guarantee in the future—and so will the choices companies have to make.

—Ed Sperling

For all the promise and subsequent anxiety about moving to the next process node or stacking die, the real problem isn’t technology. It isn’t even cost per transistor. It’s who will take responsibility when something goes wrong.

Notice the word “when” rather than “if.” Rising complexity means that chips no longer can be fully verified, so errors are a given. Some errors are worse than others, of course. In a missile guidance system, an error is to be avoided at all costs. In a smart phone camera, a malfunction is frequently forgotten when a service contract runs out.

But as the semiconductor world increasingly moves to systems on chip rather than a collection of independent chips, it will be harder to pinpoint the cause of an error. And at some point there will be critical errors that cannot be fixed with software, and there won’t be enough margin left in designs—margin costs money, takes away from performance and impacts energy efficiency at advanced nodes—to smooth over the problems.

So who takes responsibility for a chip that costs several hundred million dollars to create but no longer works? Is it the OEM? The systems integrator? The foundry? Or perhaps the IP vendor, whose IP seemed to work fine in some chips but which causes a problem because it isn’t fully characterized for a new configuration?

This has been one of the big issues raised by companies considering 3D-ICs, where stacking could create proximity effects that were never considered. But it’s also a problem in increasingly complex chips where those same kinds of effects could result in similar problems. A chip with several hundred million transistors and scores of IP blocks, multiple processors, I/O schemes and voltage islands is bound to fail somewhere.

While most engineers know not to put a noise-sensitive analog blog next to a very loud SerDes block, they may have no insight into RC delay at 14nm from the interconnect or shrinking wires. It’s also difficult to predict where electromigration will occur, even with the best extraction tools, or when fill around a transistor isn’t completely consistent and causes a transistor to malfunction. And in a very complex chip, it’s hard to even effectively map the signal path and guarantee it will work properly.

Add in multipatterning, stress effects, process variability and it’s imperative that all contributors to an SoC design—planar or stacked—begin dialog about sharing responsibility and information that can prevent problems in the first place. Communication is a first step. Understanding issues on all sides is next, based on experience of test chips. And putting in place working agreements that will allow companies to jointly diagnose and solve problems is the third piece.

Some of these agreements already exist, such as those between foundries and their closest partners. But for the industry to advance, there will need to be many more agreements hammered out. It’s not the technology that will slow down progress in this market. It’s the lawyers and the bankers. And until they no longer need to get involved, everyone will move much more slowly and carefully than progress demands.

—Ed Sperling

The increasing number of research projects under way to solve many of the thorniest issues in the history of semiconductor design and manufacturing are a testament to just how tough the job has become. Never before have there been so many technological roadblocks at the same time—and so many potential options for solving them.

Those challenges—or opportunities, as marketing execs like to call them—translate into competitive stakes. For those with the right solutions, or the wherewithal to buy them, the table stakes are now high enough that much of the industry has suddenly gone mum. Witness the falloff in papers submitted to the IEDM conference this week. Add to that the rising number of no-comments that we receive as journalists who are deeply embedded into this industry. And take note of Apple’s statement about why it’s moving some of its manufacturing back to the United States—so it can keep tighter rein on intellectual property.

It costs huge sums of money to be able to translate technological advances into a viable and competitive commercial strategy. Intel’s surprise move to add finFETs at 22nm was a prime example. The big foundries were, to put it mildly, stunned. The race to the next nodes and into stacked die and other packaging options has become just that—a race.

As you might expect, for all the tightly kept intelligence there is also counterintelligence. Misinformation is beginning to seep out into the market.
For example, because of the tradeoff between finFETs and FD-SOI, rumors have been circulating that there is only one source for SOI. In fact, there are three—Soitec, MEMC Electronics Materials Inc. and Shin-Etsu Handatai.

Add to that the numbers game being played for the next node after 28nm. Joel Hartmann, EVP at STMicroelectronics, said the roadmap calls for moving from 28nm to 14nm, but added that the new 14nm is actually 20nm. And foundries have begun mixing up process nodes to salvage their investments in 20nm technology where there are no finFETs available.

This is business as usual in a competitive market with sophisticated marketeers, but it also adds a level of confusion we haven’t seen since IBM first was accused of issuing FUD messaging—fear, uncertainty and doubt—in the mainframe business back in the mid-1970s to stymy rivals such as Amdahl. The stakes are clearly high and growing, which means the level of misinformation will grow proportionately.

—Ed Sperling

It makes sense that the first chips were built out of silicon. It’s hard to think of a more abundant material than sand, or one that’s so easily accessible in so many places. It’s like building the first homes out of earthen bricks. There was never a shortage of materials.

Even aluminum and copper for the wires and interconnects in these chips are readily available, despite the rising price of copper in recent years. And, in theory, anything that is carbon-based, such as graphene or other nanowires, should be readily available for use. Most of us burn enough toast each year to provide a steady stream of carbon for these ventures.

But as we move down process nodes, the semiconductor industry has been pushing steadily deeper into the Periodic Table using a group known as transition metals—and with mixed results. Consider element No. 73, for example—Tantalum. It has become a mainstay in capacitors, but the supply has been in jeopardy since the early part of the millennium due to mine closings in Australia, Canada and Mozambique and political uncertainties in Central Africa. And as the co-CEO of Synopsys quipped back several years ago, “Does anyone really know the world’s supply of Hafnium?”

These are more than just amusing questions. Just because an element looks good on paper based on electrical properties—its ability to resist breaking down over time under constant bombardment of electrons, in extreme temperatures, or under the stress of semiconductor manufacturing and polishing—that doesn’t mean it will be a good candidate for mass-produced chips.

The problem is that this kind of supply chain information isn’t necessarily available to researchers. Understanding what works electrically, physically and over time has nothing to do with what works in a global supply chain. At the forefront of science, anything is possible. Across a geopolitical spectrum, many things are subject to negotiation.

We’ve heard plenty about co-design and co-development, but most of this has been inside the semiconductor world. As we reach out to find new materials, we will have to forge an understanding between science and economics—is there sufficient quantity available from a stable government at a reasonable price? These are questions the semiconductor has not had to wrestle with in any serious way in the past, but as we move to new and more exotic materials, they are questions that will need to be asked.

There are 118 elements in the Periodic Table, and there are thousands of compounds and isotopes that can be made from these elements. Understanding availability and price up front would save a lot of effort and speed up research on materials that could really make a difference.

—Ed Sperling

It was nice when we had round numbers to work with. It was pretty simple to move from 180nm to 120nm and then to 90nm. Then the half nodes started—45/40, 32/28 and 22/20nm.

After 14nm we are poised dangerously over the single-digit process nodes. Intel is working on 10nm, to be followed by 7nm or 5nm. Other companies are looking at 11nm, to be followed by 8nm, 6nm or something even further down the road.

So why so much confusion over which is the real next node? The answer, depending upon who you ask, doesn’t appear to be grounded in anything other than marketing and some rather vague measurements that don’t seem to be the same from one foundry to the next. If you can do 20nm it’s assumed to be better than 22nm, even if in reality you’re only doing 20.5 or 21.5. And if you can offer more instructions per second or more cores its considered better than if you can offer fewer—regardless of whether a particular application can take advantage of either of them.

This is about to hit an entirely new pitch (no pun intended) when we get to stacked die. If you can add a 14nm processor core into a proven stack of analog and memory, replete with finFETs (at least somewhere on the chip or in the package), SOI substrates (also somewhere on the chip) and massive pipes for processing (even if they’re not used) then who’s going to question it. Most of this stuff gets delivered as a black box to chipmakers and integrators, anyway. If it can be marketed more effectively, all the better.

The big fear isn’t that we can’t hit 4nm because it’s technologically impossible. It appears that the roadmap for some chips will extend beyond the nanometer range and well into Angstroms. New atomic structures will replace ones we use today and everyone will scoff at the days when we even considered etching masks with EUV, and designs will be based upon manipulation of subatomic particles that are still in the realm of theoretical physics. At 10nm or so we’ll move into the quantum world, and that will become the future—at least for awhile.

But all of this hedging over exactly what number comes next will become important for a couple reasons. One is that everything inside a chip needs to be measured, and metrology is supposed to be a very exact science. Mathematicians like to brag that their area of expertise is the only exact science. Maybe, but applied math isn’t so exact—particularly in the hands of marketers. And second, these chips need to be designed and verified, and the world of back-end metrology is rapidly moving forward into the design process because of the risk of getting something wrong.

These two worlds need to meet on some very exact numbers that are relatively standard, and they need to integrate with other very exact numbers. Right now it’s hard to build confidence in numbers that seem to change with the wind.

—Ed Sperling

The sheer number of off-the-shelf parts that are showing up in ICs these days—and that includes both hard and soft parts—means that to a large extent we are designing and manufacturing a series of interconnected black boxes.

Black boxes, at least in theory, are a major time saver. The idea that you can put together a series of well-designed, state-of-the-art Lego-like blocks that are proven in silicon, yield sufficiently, and which are characterized well enough so that the physical effects and proximity effects can be taken into account in a design can be a very good thing.

Reality is somewhat different, though, particularly at advanced process nodes and in stacked die. Black boxes can turn bad on their own, and they can start out good and perform miserably when combined with other black boxes. Known good die is the widely discussed problem, but even within die there may be known good blocks that don’t work together.

The problem is that you can’t characterize effectively if you don’t know everything else that’s going around a subsystem or IP or even a die in a stack. The creator of the black box has no idea how their technology will be used, what it will be next to, or even what process node it was created in. They can’t hope to understand the end usage model except as it’s defined by a bell curve, and if their parts are going into very advanced nodes they don’t know how process variability, stress and physical effects will work individually and in combination.

There’s no magic bullet here, but testing to the point of confidence is at least a step in the right direction. That test needs to be part of the initial design architecture, and it needs to follow right through to the manufacturing because there’s no such thing as a single test. Testing needs to be internal, external, and in stacked die it needs to be done before and after packaging. If there’s no way to test it after the package is sealed, then it’s a series of black boxes within a black box with no direct way back in.

Like any other business, it’s one thing to trust your business partners. It’s quite another to trust them blindly and not hold them accountable. The semiconductor business is no different, except that for years ensuring accountability was left to the manufacturers or the design teams. It now has to be part of every process and every facet of design through to final packaging—and parts within parts within other parts need to be included. Things have become that complicated, and test has to work across all of them.

—Ed Sperling

By Ed Sperling
Throw out the most optimistic and the most pessimistic predictions about the future of the foundry model and you probably arrive at a reasonable approximation of how things will actually play out.

It’s clear that the number of customers at the front end of process technology will shrink after 20nm. It simply costs too much to design and manufacture a chip, and there aren’t enough markets capable of offering sufficient return on investment. The trend is toward smaller, fragmented markets, not one or two megamarkets. It’s also likely that the amount of money that needs to be invested in fabs after 20nm for planar SoCs may never be fully recouped, which explains Intel’s recent spate of investments in other companies.

That doesn’t mean there won’t be progress in either manufacturing or design, however, and it doesn’t mean there won’t be a need for lots of very expensive equipment. The next step is stacking of die, which already is under way. The semi industry is likely to do a double hop to 3D-ICs, with 2.5D being a commercially viable step in the short term and volume production in real 3D sometime in the second half of the decade. Exact timing depends on a number of factors, including progress in lithography, maturation of TSVs, the ability to control leakage and deal with heat caused by that leakage, and ecosystem standards that prevent a lot of finger-pointing when something does go wrong.

This represents an enormous opportunity for both manufacturing and design, rather than a reduction in new opportunities. Being able to accurately place TSVs on a substrate, to fuse together various die properly, to thin them to exact measurements—nanometers rather than millimeters—and to test them is every bit as complex as building planar devices. But it also provides a huge degree of freedom to chipmakers because it allows them to use whatever process node makes sense for a particular part of an SoC.

Still, it does raise the specter of competition from other sectors. The stakes are high and this is an inflection point. While it’s doubtful there will be a huge change on the equipment side, because of the cost of developing new equipment is enormous, it’s almost inevitable that there will be a scramble on the manufacturing side. The foundries have already offered a peak of their strategy by jealously safeguarding the interposer technology they have developed, and OSATs are scrambling to do the bonding and testing for stacked die.

IDMs are likely to get involved, as well. Intel has created a commercial foundry operation, and Samsung has been offering foundry services to large customers for some time. It’s too expensive to run their fabs partially full, as they did in the past, and they need customers to help bear the costs. Those costs will likely increase as 3D stacking gets rolling, although the amortization of those costs likely will be dragged out because a 22nm process may get fused together with a chip that was made with 14nm process technology and another one—perhaps an analog sensor, for example—at a new, low-power 130nm process.

The biggest question marks are in lithography. Does the industry move to multipatterning, commercially available EUV, directed self-assembly, or some combination of all of the above, with e-beam and gridded design rules thrown in for good measure. The future will be some combination of all of the above, shaving costs wherever it makes sense and adding them in other places where volume and efficiency can be justified.

This is hardly a scenario for doom and gloom, but it isn’t necessarily a step up for everyone involved in the supply chain. The real question isn’t whether the foundry model is doomed and whether equipment spending is over. It’s who will reap the biggest benefits from these shifts and be able to call the shots in the supply chain. So far that isn’t clear, but the posturing and positioning is already beginning.