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IP Subsystems: Is It A Catalyst for Leading Edge Design Enablement

by Jim Feldhan

The System-on-Chip (SoC) market has been successful because of the increasing use of 3rd Party Semiconductor Intellectual Property (SIP). SoC designers now look to move up a layer of abstraction to design with system level functionality in order to reduce the effort and cost associated with complex SoC designs. By doing so, SoC designers can add higher levels of system functionality and cutting-edge feature sets without needing to design these functions at the absolute lowest level of complexity.

The IP subsystem is a methodology designers are employing to infuse the right level of complexity and functionality to meet rapidly changing market requirements without experiencing a corresponding increase in design costs or design cycle time.

The market entry by Cadence, Synopsys, Sonics and Analog Bits over the past 12+ months marked a turning point in the IP subsystem era. Semico expects to see a competitive market for 3rd party IP subsystems in the follow areas:

  • Computing subsystems
  • Memory subsystems
  • Video subsystems
  • Communication subsystems
  • Multi Media subsystems
  • Storage subsystems
  • Audio subsystems
  • Security subsystems
  • System Resource Management subsystems

The changes being implemented in the SoC design methodology today reflect issues the industry has been grappling with for the last 5 – 6 years. Does an IP subsystem solve or mitigate some of the follow issues?

  • Rising design costs
  • Increasing design complexity
  • Shrinking market windows
  • Lengthening design cycle times
  • Rapidly changing market requirements
  • Escalating integration costs for SIP blocks
  • Software design costs exceeding silicon design costs

Semico believes they will help find new ways to develop fresh SoC solutions. The complexity confronting SoC designers at the monolithic silicon level today closely mirrors the complexity system designers were putting into their products at the discrete semiconductor level only a few short years ago. Where can we expect the IP subsystem market and the broader SoC market to evolve to over the next few years?

The advent of the IP subsystem market is a prime example of the trends that have driven the semiconductor industry from day one: evolution, integration and innovation. It is reasonable to expect these underlying market drivers will continue in force over the foreseeable future. It is entirely likely the pace of innovation will not stop and evolutionary forces will continue to ratchet up the progress of integration displayed by the new IP subsystem concept and the products it delivers to the market.

Semico is hosting a one-day conference on the IP Ecosystem in San Jose at the DoubleTree Hotel on Nov 6th, 2013. A panel discussion on the topic of Designing for New World Applications will delve into topics such as software, verification, and subsystems. Moderated by Mahesh Tirupattur of Analog Bits, the panel will explore design solutions for the future. Participants include Jason Polychronopoulos, Mentor Graphics, Warren Savage, IPextreme, Chris Rowen, Cadence, Suk Lee, TSMC.

If you’re interested in participating in this discussion, have something to add or just want to hear what others are doing, register for Semico’s IP Conference by using the following link http://tinyurl.com/kwundyd .

One Response to “IP Subsystems: Is It A Catalyst for Leading Edge Design Enablement”

  1. Blog Review: October 28 2013 | Semiconductor Manufacturing & Design Community Says:

    [...] Intellectual Property (SIP). Jim Feldhan of Semico notes that SoC designers are now looking to move up a layer of abstraction to design with system level functionality in order to reduce the effort and cost associated with complex SoC designs. By doing so, SoC [...]

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