Semiconductor Manufacturing & Design Community » White Papers

EUV Flare And Proximity Modeling And Model-Based Correction

ed — Thu, 16 May 2013 07:01:14 +0000

The introduction of EUV lithography into the semiconductor fabrication process will enable a continuation of Moore’s law below the 22 nm technology node. EUV lithography will, however, introduce new and unwanted sources of patterning distortions which must be accurately modeled and corrected on the reticle. Flare caused by scattered light in the projection optics is expected to result in several nanometers of on-wafer dimensional variation, if left uncorrected. Previous work by the authors has focused on combinations of model-based and rules-based approaches to modeling and correction of flare in EUV lithography. This paper focuses on the development of an all model-based approach to compensation of both flare and proximity effects in EUV lithography. The advantages of such an approach in terms of both model and OPC accuracy will be discussed. In addition, the authors will discuss the benefits and tradeoffs associated with hybrid OPC approaches which mix both rules-based.

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Mask Data Preparation Flow For Advanced Technology Nodes

ed — Thu, 18 Apr 2013 07:01:21 +0000

The trend to reduce critical features dimension has dramatically increased design file size. Design tape–out flows at the 28 nm technology node handle post-OPC data files that reach hundreds of gigabytes. This trend increases at 20 nm and below. That predicts new challenges in mask data preparation flow for advanced technology nodes. We have developed a mask data preparation flow to tackle the challenge of maintaining a consistent delivery time to mask shops, while efficiently using exiting hardware. Taming data file size required innovations in data processing for fractured data files creation and also in data review techniques. The paper will discuss these innovations and conduct a demonstration with results in a 28 nm technology node production flow. Cost-benefit analysis will be illustrated with runtime comparisons of fractured data creation, and data review between traditional mask data preparation flows and this specific flow.

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Computational Lithography

ed — Thu, 21 Mar 2013 07:01:09 +0000

Computational lithography has become an integral part of design since the 130 nm process node. New techniques continue to be developed to extend the steady node shrink year after year.

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Next-Generation Signoff Analysis

ed — Thu, 21 Mar 2013 07:01:25 +0000

The electronic design industry continues to push the limits of moore’s law through smaller and smaller process nodes. As we reach 45nm, manufacturing and process control becomes increasingly difficult, making it imperative that manufacturability issues be addressed much earlier in the design cycle to avoid costly respins and chip failures.

Physical and electrical effects at this node challenge both design closure and time to market, and the requirements for design signoff are changing in order to address the inherent manufacturing and process variability. Naturally, this situation can seriously undermine the manufacturability of the design. In fact, a paradigm shift is evident in the all-important signoff analysis step of the digital design cycle.

At issue are the levels of validity and confidence that can be reached with today’s Ic design closure and signoff methodologies. designs that pass traditional sign-off standards might still fail in 45nm silicon. In contrast, using excessive guard-bands or over-conservative margins to satisfy traditional static timing analysis (sTA) signoff regimes can negate the benefits that smaller process geometries offer.

This paper looks at some of the electrical, physical, and manufacturing challenges to current signoff analysis methods, and shows new ways to improve predictability, productivity and performance at the 45nm process node. using these new methodologies, designers can prevent silicon failures and better manage timing, leakage power, and signal integrity–both across a wafer and across the surface of a single chip.

Optimizing Test To Enable Diagnosis-Driven Yield Analysis

ed — Thu, 21 Feb 2013 08:01:59 +0000

Using diagnosis-driven yield analysis, companies have decreased their time to yield, managed manufacturing excursions and recovered yield caused by systematic defects. Dramatic time savings and yield gains have been proven using these methods. Companies must plan ahead to take advantage of diagnosis-driven yield analysis. The planning needs to include how and what patterns to generate during ATPG/DFT, what design data to archive, how to optimize your test program, how much data to collect, and what/how much diagnosis to perform. This white paper will address how to optimize the test environment in order to enable efficient diagnosis-driven yield analysis.