EUV will introduce unwanted patterning distortions that must be accurately modeled and corrected.

How to tame data file sizes, address fractured data files creation and streamline data review techniques.

Enabling 12 technology nodes in 12 years.

Best practices for tackling electrical, physical and manufacturing challenges.

Decreasing time to yield requires planning for what patterns to generate, what data to archive and hot to optimize your test program.

A look at how to reduce custom/AMS design cycle time while improving design quality with on-demand, in-design signoff-quality verification.

Double patterning marks a turning point in terms of lithography, variability and complexity.

A look at the challenges and various solutions using LELE at 20nm, including place and route effects, OPC and mask misalignment and image rounding.

Getting more functionality on the same die area using more and increasingly complex verification rules is getting more difficult. Here are some solutions.

At 15nm and beyond, printing of pitches of 64nm and below will be required, and for EUV to replace ArF multi-exposure approaches patterns will have to be printed in a single-exposure process.