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White Papers Archive

RF-SOI Wafers for Wireless Applications

The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.

DFM: What is it and what will it do?

Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.

Via Doubling to Improve Yield

In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.

The Impact Of 14-nm Photomask Uncertainties on Computational Lithography Solutions

Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.

A Study Of Model-Based Etch Bias Retarget For OPC

The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.

Automation of Sample Plan Creation For Process Model Calibration

A look at ways to simplify the optical and resist model calibration and to speed up the entire process.

Extending Copper Interconnect Beyond The 14nm Node

Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.

3D-IC Testing With The Mentor Graphics Tessent Platform

Testing interposer-based versions of stacked die and future versions using through-silicon vias.

EUV Flare And Proximity Modeling And Model-Based Correction

EUV will introduce unwanted patterning distortions that must be accurately modeled and corrected.

Mask Data Preparation Flow For Advanced Technology Nodes

How to tame data file sizes, address fractured data files creation and streamline data review techniques.