For the most part, cell libraries designed for processes that don’t require double patterning layers are placement-independent. This independence allows the cells to be very compact, while providing maximum flexibility for the place and route (P&R) tools to minimize area utilization. With the need for double patterning layers at advanced nodes, this placement independence of very compact cells no longer can be taken for granted, even when each cell is DP-clean. Figure 1 provides a simple example of how a double-patterning error can occur on a single interconnect layer with two different DP-clean standard cells.

Figure 1: Two DP-clean cells can form an odd cycle violation when placed adjacent to each other.
Each cell contains a VDD strap across the top and a VSS strap across the bottom. The arrows represent spacing between shapes that require color alternation. Each cell by itself has no DP violations, as there are no odd cycles within each separate cell. However, when the cells are placed adjacent to each other, the spacing interaction between a polygon in each cell forms an odd cycle crossing the cell boundary. Because of this DP restriction, these two cells cannot be placed directly next to each other, limiting the flexibility of the P&R tools.

One potential solution to this problem is shown in Figure 2. The original two cells (Cell A, Cell B) were modified (Cell A’, Cell B’) to add extra space to the left and right borders of each cell. This space avoids the creation of the odd cycle when these cells are placed next to each other, but it also makes the cells wider, increasing the design area.

Figure 2: Modifying the width of the cells avoids odd cycle violations in abutting placements.

However, adding this extra space on the left and right borders of the cells still does not guarantee placement independence in DP design. Figure 3 shows the modified Cell A’ from Figure 2 placed next to a new Cell C. Both of these cells have extra space on the left and right borders, so there is no spacing arrow between the nearest neighbor polygons at the placement abutment. However, an odd cycle that traverses through the power and ground rails has been formed across these two cells. Because the interior polygons interact at minimum spacing with the power and ground polygons, odd cycles like this can occur.

Figure 3: Odd cycles formed between cells through the power and ground rails.

Figure 4 demonstrates the simplest solution to this new issue. By adding additional height to the cells (so that the interior polygons have more than minimum spacing to the power and ground rails), these odd cycles can be eliminated.

Figure 4: Cells with height and width modifications to avoid odd cycle violations in abutting placements.

Of course, the downside of using these two solutions is that we’ve now added area in both the vertical and horizontal direction. So, a tradeoff has been made between increasing the area of the cells in the library and the placement freedom of the P&R tools.

An alternate approach to solving these DP-aware placement issues with anchoring is shown in Figure 5. In this example, we use color anchors to force specific color assignment to the polygons on the outer border of the cells. The color selection has been chosen so that any cell can be placed next to any other cell without causing a same color spacing error. This allows us to design the cells with minimum vertical and horizontal area, but still have them be placement independent.

Figure 5: Border color anchoring technique for assuring placement independence.

However, implementing this approach can be a complex process, with multiple limitations that must be carefully managed:

1. Forcing boundary polygons to a particular color introduces spacing restrictions within the cell. For instance, on the left border of Cell A, the two small polygons and the power rail are assigned to the blue color. Because all of the polygons on this edge and the power rail must be constrained to the same color, they cannot be at minimum space between each other without causing a same color space violation.
2. Anchor path violations can potentially occur between the anchored polygons on one edge of the cell and the anchored polygons on the other side of the cell. This again limits the flexibility of the interior design of the cell. These limitations can potentially lead to larger area cells, negating the value of this approach.
3. The forced anchoring of one color to the left side and the other to the right side prevents the P&R tool from flipping cells, limiting some of the tool’s placement flexibility.
4. Finally, given all these conditions, a practical automated means of guiding designers through the implementation of such a strategy is extremely difficult. Realistically, designers are forced to manually set the appropriate anchors and hope that they did it correctly.

There is one more option (with two variations) that enforces a “framing” methodology, similar to the anchor technique. Figure 6 demonstrates the first variation of this approach to guiding cell design. A temporary “frame” of anchored polygons is placed around the borders of the cell. Because of their spacing to the cell borders, these polygons enforce a particular coloring onto the cell polygons at the edges. These anchored polygons are only temporary, and are removed once the cell design is complete. If automated color coloring is applied to this cell, these frame anchors force the cell polygons to be colored similar to the border coloring methodology shown previously.

Figure 6: Use a temporary frame of anchor polygons to force a particular coloring of the IP before placing in the full chip.

A more flexible approach is the second variation, which uses a colorless temporary frame when designing a cell (Figure 7). DP odd cycle checks run against a cell design with this type of frame layout ensure that the VDD polygon is the opposite color to the VSS polygon, and that all left border polygons are the opposite color of the right border polygons, without actually anchoring any of them to a particular color. This approach allows us to leave the cells in an uncolored state, but still guarantee placement independence.

Figure 7: Use a frame of colorless polygons if you plan to leave the IP colorless in the full chip.

In the end, there are many options to placement-friendly DP-aware standard cell design. All of them involve potential trade-offs between complexity of design, cell area, placement independence, and ultimately die size and time-to-market. While the technique you choose to use will be determined by your organization’s structure and processes, as well as your own experience with and knowledge of DP design, the one thing you can’t afford to do is wait until layout to consider these DP issues. If you do, you will surely be caught between a rock and a hard place, and your design schedules will feel the pain. Work through these issues early (before your design teams start doing layout), and enforce an intentional methodology that meets your particular business goals. You’ll find yourself in a much more comfortable position, I promise.

In my next article, we’ll look at how DP affects the routing methodologies.

—David Abercrombie is the Advanced Physical Verification Methodology Program Manager at Mentor Graphics.

By David Abercrombie
As I discussed in my previous article, the use of stitching can greatly reduce the number of double patterning (DP) decomposition violations that a designer has to resolve. However, stitching also adds significantly increased complexity—the decomposition tool must process many additional design rules to generate legal stitches and know how to use them properly during coloring. Figure 1 illustrates a few of these rules.

Figure 1: Rules constraining stitch insertion during decomposition.

The initial challenges to automating stitch generation and layer decomposition are: 1) capturing these constraints within the syntax of the tool language, and 2) adhering to the complex combination of rules. Figure 2 shows how various rules affect the determination of where a valid stitch candidate can be generated. The separators themselves determine locations where stitches cannot be placed due to spacing constraints (because a stitch contains both colors, it always “violates” a spacing constraint between two colors). Minimum area constraints mean you can’t place stitches too near the end of a line. And certain types of corner stitches are not allowed, such as the elbow in this example. Once you’ve applied all those constraints, you are left with the potential stitch locations. But a stitch is not allowed in one of those locations, because the stitch itself must have a certain required overlap (minimum length). In the end, you are left with only two possible stitch candidates.

Figure 2: How design rules affect the determination of valid stitch candidates.

Even more complexity arises when the creation of a stitch introduces new separator requirements. Think of it as a “chicken and egg” problem—you need to know what separators exist to know where a stitch can go, but adding a stitch can introduce new separators. As shown in Figure 3, one stitch can exclude the validity of another stitch, or introduce color separation requirements between shapes that previously did not have color separation requirements.

Figure 3: How the insertion of stitches can introduce new separator constraints.

Despite these immense complexities, it has been possible so far to produce automated tool functionality that captures and applies all of these rules to produce successful layer decompositions. However, capturing these rules in a tool requires the creation of specific syntax in the programming language for each rule type. Although it is easy for a user to modify specific aspects of a given rule type, and to add multiple versions of each rule type without affecting tool capability, new rule types require tool enhancement. The biggest problem with DP in the industry right now is the rapid rate of rule changes while new processes are in the early stages of development and process maturation. This rate of change delays the implementation of new rules into a PDK, because engineers must wait for the vendor to enhance the tool and release a new production version.
For this reason, a new approach to implementing these capabilities in the tool is required, one that allows more flexibility. In a nutshell, the requirements for a good decomposition algorithm are:

1. Capture all DRC rules (constraints) associated with the generation of a legal stitch;
2. Decompose the layout and determine the odd cycles;
3. Generate a stitch wherever needed to break odd cycles;
4. Minimize the number of stitches needed to eliminate conflicts, and
5. Highlight remaining cycle violations where a legal stitch was not possible.

The traditional EDA approach is to combine all of the above requirements into a single operation that generates the stitches and colors the layout. To make this method work, all DRC rule types must be coded into the core of the tool. If a new rule type is added, a change in the core code is mandatory, creating a delay in the tool development and release cycle.

Particularly in the early years of a process development, it is not reasonable to assume that the rate of tool development will always be faster than the rate of the need to adopt new design rule types. For this reason, we can separate the process into two steps, as shown in Figure 4. In the first stage, all the regions where a stitch can be placed while honoring all the design rules are marked. In the second stage, the layout is decomposed using only those stitches that will resolve DP conflicts.

Figure 4: The new two-step approach to decomposition with stitches.

The benefit of breaking this process into two steps is the opportunity to insert custom layer derivation operations within the coding of the decomposition function. These custom code insertion points enable the deck writer to generate additional stitch candidates (or filter existing stitch candidates) to meet new rules that must be considered, but are not yet natively captured in the tool syntax. Figure 5 illustrates this new flexibility.

Figure 5. Customization opportunities available in a two-step flow.

In this customized flow, we now can define custom constraint layers that will affect the behavior of the stitch candidate generation before generating the stitch candidates. After stitches are generated, we can filter out stitches or derive additional new stitch candidates to accommodate new rules. Before the decomposition step, we also can define customized separators (if necessary) and pass them to the splitting step. Finally, after the decomposition is run, we can modify the generated colors (if necessary) to meet new rule requirements.

The benefit of this flow is the ability to accommodate the high rate of rule changes early in the process development much more effectively, while allowing sufficient development time for building and testing new native support functionality in the tool. As the native functionality becomes available, the customization code can be removed. This also enables the foundry to qualify a decomposition solution without having to wait for the final tool development. Overall, a mutually beneficial situation is created that allows rapid response time for the customer and appropriate tool development time for the EDA vendor.
This flow has already been used on 20nm technology node layers with excellent results. For end users using the PDK deck for cell and chip design, the experience has been the following:

1. There is no noticeable difference in execution or results output visible to the designer, regardless of how much customization versus native functionality is used in the deck.
2. The decomposition still takes place automatically.
3. Any odd-cycle or anchor-path violations that are not fixed by stitches are displayed normally.
4. Mask coloring output layers are generated normally.

No matter how fast we have to run to keep up with the development of DP design rules and checks, the two-step decomposition flow can keep us one step ahead.
In my next blog, we’ll start looking ahead to the multi-patterning challenges and solutions coming with 10nm process technologies.

—David Abercrombie is the Advanced Physical Verification Methodology Program Manager at Mentor Graphics.

Figure 1. Fill has become highly complex, and is used to address many manufacturing issues.

Two primary new concepts of fill at 20nm, particularly for SoCs, are 1) it must be process-accurate, and 2) it requires a hierarchical methodology.

Process-accurate fill
Fill affects numerous aspects of manufacturability. Fill must be correct-by-construction, meaning the fill engine and analysis engines are integrated. It must comply with double patterning rules, forbidden pitch requirements, use cell-based process-validated fill patterns, and be timing-aware. Given the tight manufacturing constraints, fill for back-end layers and for front-end layers must be done by a foundry-certified fill utility, which requires both the fill rules deck and the fill software programs designed for the N20 process. There is no way around this fact. The foundries expect your GDSII to be filled with their foundry-certified fill utility, which have been developed in lock step with the manufacturing process.

Given the new complexity and importance of fill, the foundries want to make fill easier for you. Take double patterning: For fill layers, double patterning reduces manufacturing variability by balancing the light emitted through the mask, and leveling the impact of etch on the design. The foundry-certified fill deck and software makes double-patterning decomposition transparent. The complexity of fill is hidden—from the number of new rules required, to the merged fill/analyze processes—to reduce the impact of fill on the entire design team.

Change in fill methodology
One impact that the foundry-certified fill utilities can’t hide from you involves the changes to fill methodology that are needed for SoCs at N20. In the past, fill was added at the time of chip assembly, and then to the entire layout at once. Place and route tools usually added some fill to blocks before the SoC was assembled, but that fill acted as a sort of placeholder to help estimate density and timing/power impacts. It typically was stripped out so the more accurate fill could be added during the final full-chip verification and signoff steps.

This flat flow, in which fill was added to the top-level design, is a thing of the past. Why? Because of the growing design sizes. For N20, we expect design sizes of 100 billion to 200 billion transistors, and we expect to use much more fill to meet the manufacturing requirements. Consider this: For large SoCs at N20, the design size after fill is on the order of 5x the pre-fill design size. That’s a lot of fill. The only way to handle that much data is to first complete the fill for each block in the design before attempting top-level fill.

This hierarchical flow, with block-level fill done before top-level fill, is the only solution for managing file-size and run-time. In a hierarchical flow, top-level fill is for intra-block areas, and to touch up block-level fill once the blocks are considered in the top-level context. Mentor’s fill technology, called SmartFill, addresses all fill constraints—not just the basic minimum and maximum density constraints, but also the more advanced gradient (density difference in adjacent windows) and magnitude (density difference in windows across the design) constraints. SmartFill also balances the need to satisfy the constraints while minimizing the amount of areas with no fill with the smallest parasitic impact. SmartFill is able to achieve this balance and minimize the timing impact by reading a list of your critical nets so it avoids interfering with their performance by adjusting the spacing of fill shapes around these nets in both the lateral and vertical directions.

As a final note on fill methodology, your fill solution should integrate easily into your existing design flow. SmartFill, for example, is a Calibre product, so it plugs right into any existing Calibre flow. It also can read and write to multiple design databases (such as LEF/DEF, Open Access, and Milkyway), which ensures your fill flow will work with any major design implementation flow. The read capability allows the filling engine to make informed fill placement decisions (based on both the type of signals and which are timing-critical), while the write capability enables you to verify the design with fill in your signoff timing flow.

—Jean-Marie Brunet is the Product Marketing Director for Litho Friendly Design (LFD) and Design-for-Manufacturing (DFM) Products at Mentor Graphics Corporation.

—Jeff Wilson is a DFM Product Marketing Manager in Mentor Graphics’ Calibre organization.

Believe it or not, that’s a viable approach…if the “hospital” you use gives you operating privileges. The correction technique is called “cutting and stitching,” although you will often just hear it referred to as stitching (guess some engineers are just squeamish). Let’s take a look at how it works. Figure 1 shows a couple of classic layout configurations that cannot be decomposed properly into two masks.

Figure 1: Self-conflicting and odd-cycle DP errors

The top row shows a single polygon that has minimum spacing conflicts with itself. In other words, the highlighted minimum spaces are not allowed between polygon edges unless the edges belong to polygons on different masks. Because all the polygon edges involved in the minimum spaces belong to the same polygon, they have to be on the same mask. The only correct solution is to increase these spaces, which requires more design area. The bottom row shows an odd-cycle error. These three polygons cannot be alternated between two masks, because you can’t divide three by two without a remainder.

However, by slicing a polygon into two or more pieces (okay, it’s called a “cut”), both of these error conditions have a DP solution, as shown in Figure 2. Now, one piece of the original polygon can be defined by one mask and the other by the second mask. In the top row, the polygon edges forming the minimum spaces now belong to different masks, making them legal. In the bottom row, the bottom polygon of the three is “cut” into two pieces, creating a legal, even cycle. The benefit is that the errors are corrected without increasing the design size. In fact, the basic design is not changed at all.

Figure 2: DP cut solutions

If this sounds like magic, you aren’t too far off. We have seen cases in which 90% to 95% of a design’s DP errors can be fixed using cuts, while leaving the design essentially unchanged from a circuit layout and area perspective.

Of course, nothing comes for free, so it’s time for the fine print on the medicine bottle. As we discussed previously, because the DP process uses two separate lithographic printing steps to define the one design layer, there can be misalignment between the two lithography contours, in addition to the lithography rounding effects inherent to all designs. Figure 3 shows how this potential misalignment can negatively impact the use of cuts to fix DP violations.

Figure 3: Potential lithographic misalignment with DP cuts

As you can see, the two pieces that originally touched at the cut location may not make a robust connection after each piece is rounded during imaging, then misaligned relative to each other. This would, of course, cause an open circuit in your design, which is unacceptable. So how do we “heal” a cut? To overcome this issue, we extend the two pieces of the original polygon to overlap at the cut location. This overlapped area is called a “stitch,” and as you can see in Figure 4, it provides margin against the lithography rounding and misalignment concerns.

Figure 4. Avoiding misalignment issues with cut and stitch

Figure 5 shows a more realistic layout that has several DP odd-cycle and anchor-path violations (marked by red and yellow error rings) that would normally require spacing adjustments to fix. Using stitches, you can see that most of the errors are corrected.

Figure 5: Fixing odd-cycle and anchor-path violation using cuts and stitches

You may be asking at this point why the remaining error could not also be fixed using a stitch. Well, that’s the second caveat in the fine print. You can’t just put a stitch anywhere. Like anything else in a layout, there are many design rules associated with forming stitches. Stitching adds a whole new level of design complexity to the rules that guarantee robust electrical functionality in manufacturing, and it can be difficult for a designer to determine how to create a “legal” stitch that meets all of these extended rules. Precisely because of this added complexity, not all foundries offer the option for using stitches.

One design-side solution for this complexity, like many challenges in IC design, is to push the complexity into the EDA tool. That’s exactly what we’ve done at Mentor with the Calibre Multi-Patterning tool. We built automated functionality that can generate stitch candidates that comply with all the design rules, and that can be evaluated with our decomposition and checking tool to identify and solve DP errors.

In my next blog, we’ll examine the types of rules associated with generating stitches, and how EDA automation enables support for the ever-changing set of rules and makes utilization of stitching possible in 20nm design. I promise there will be no blood…

—David Abercrombie is the Advanced Physical Verification Methodology Program Manager at Mentor Graphics.

The new DRC and DFM requirements for 20nm are aggressive—more numerous and complex than ever. The 20nm design rules demand fill shapes in greater numbers and require them to be evenly distributed. In addition, there is the complexity of multi-layers fill shapes that need to be optimized based on constraints such as density and perimeter. This all leads to a greater variety of fill shapes. Even the single layer shapes have greater complexity, with double patterning adding a new dimension to fill. For drawn layers, double patterning improves printability. For fill layers, double patterning (figure 1) reduces manufacturing variability by balancing the light emitted through the mask and moderating the impact of etch on the design. The task at hand is to balance the growing fill requirements while also controlling turn-around-time of the fill process.

Figure 1. Double pattern has extended to fill shapes. The goal is to improve process variability effects.

To solve these challenges, you need a team effort from the foundry, EDA vendor, and customer. I’ll explain the role of each player in the ecosystem.

The Foundry and the EDA Vendor
Interactions between the EDA vendor and foundry start early in the process development cycle. Mentor is the de facto standard and has long-standing collaborations with all major foundries, so that new process rules and tool development happen in lock-step. The foundry creates the rules, honing them to address the limitations of the process. The rules are written into rule decks in the industry-standard SVRF format. The new technology requires the foundry to worry about novel effects that have never before been cause for concern, and they need to partner with EDA vendors in order to help define and understand what the fill tools are capable of doing. This collaboration has two direct benefits: 1) rules can be specified in such a way that make the checks possible, and 2) when new functionality is needed, such as double patterning, this information needs to get to the EDA vendors early in the process so that they can provide a solution. Being the golden solution makes a significant difference in that relationship.

During the yield ramp period, it is very important that new rules can be addressed, but it is also important to make the decks sustainable. This includes being able to easily update the decks when the structure of the fill shapes or spacing changes occur. It has become clear that at 20nm, the fill solution must raise the level of abstraction above the polygon level. The complexity of the fill shapes calls for a ‘cell-based’ fill solution that helps manage the complexity of multiple layers and the sheer number of shapes added. This ability to place fill cells rather than individual polygons significantly speeds up deck development and reduces runtime and output file size.

The EDA vendor, at this early point, starts developing the tools and technology to implement the process requirements. With foundry input, Mentor developed new core algorithms for fill at 20nm that make the fill process easier, including adding commands that raise the level of abstraction for the filling operations, and adding keywords for basic operation such as double patterning and forbidden pitch checking.

Another task for the EDA vendor is to ensure fast and accurate fill. The time required for fill is largely driven by the sheer number of fill shapes being added to the design. To reduce the run time, concurrent analysis and fill is needed. The Mentor analysis tools are built on the Calibre platform so that fill and analysis are done with the same signoff engine. This allows for a single-pass, correct-by-construction fill process.

The partnership between the foundry and the EDA vendor is absolutely essential for getting the 20nm technology in place and ready to roll out to customers. Mentor bridges the gap between the foundry and the customer by maintaining close relationships at the foundry and by using the same core engine for fill, as well as the golden signoff checker that the foundries uses.

The Third Leg of the Fill Ecosystem: Designers
Successful fill at 20nm also depends on using real design data to validate the work the EDA vendor and foundry have done. Once the process rules are in place and validated, the designers assume responsibility for fill in partnership with the EDA vendor. The fill solution must provide some key features: push-button, correct-by-construction flow, predictable and reasonable run time, smaller file sizes, accuracy, and flexibility to fit within any physical implementation flow.

The correct-by-construction requirement is met by using the same engine for both fill and for analysis. Run-time is further addressed with the cell-based fill technology developed to achieve the demands of the latest technology nodes. Calibre interfaces with all leading design environments and enables feed-forward and back-annotation flows. The feed-forward capability allows the filling engine to make informed fill placement decisions (based on both the type of signals and which signals are timing-critical), while the back-annotation enables customers to verify their design with fill in their signoff timing flow.

Figure 2. The Calibre Yield Enhancer product with SmartFill can be accessed from within the major place and route tools, including IC Compiler, Olympus-SoC, and Encounter.

The designers fill solution must work with the industry-leading design tools, including place and route tools as well as full custom environments (figure 2). This is important because of the revolving door that exists in the place and route world. Calibre has been the de facto standard for over 10 years, but there have been at least four market-leading place and route products in the same time span.

Summary
The 20nm fill requirements from the foundry go far beyond simply adding more polygons; fill is now done with a cell-based approach that supports multi-layer fill, complicated spacing rules, and automated double patterning. These challenges require a joint effort built on trust and experience. Mentor partners with all major foundries to make a fill solution for 20nm and beyond that not only meets the new stringent manufacturing requirements and design constraints, but is easier to use, has smaller file sizes, faster runtimes, and integrates into multiple design flows.

—Jeff Wilson is a DFM product marketing manager in the Mentor Graphics Design to Silicon division.

Even though this methodology does not require the designer to generate two colors, there are situations in which the designer may want to know what the color assignments will be.
The first situation is the case where the designer is purely curious. Curiosity is a common trait in most engineers, so this is to be expected, but it probably doesn’t warrant a change in the design methodology. In the second situation, a designer is trying to debug DP errors, and believes that seeing the colors will enhance the productivity of error resolution. As reasonable as this may sound, seeing the colors will most likely degrade debug productivity, which is a surprise to most people.

Let’s look at two examples to explain why this paradox is so. The most common type of DP error is the odd cycle violation, in which an odd number of polygons require color alternation in a way that cannot be resolved. Figure 1 shows an example of an odd cycle violation among three polygons. As indicated by the black arrows, each pair of shapes in the set of three require opposite color alternation between them. The DP error highlighted by the red ring indicates there is no valid coloring solution for these three shapes, meaning any color solution displayed to the designer would, by definition, be incorrect. Not only that, but the particular colors displayed would be only one option out of many equally incorrect set of colors that could be shown. All of these coloring options cause a DP separator to be violated, as indicated by the red error line, so they are all equally incorrect.

Figure 1: Odd cycle DP violation, with all possible (but incorrect) DP coloring options.

By showing the error as a RING, minus any colors, the designer is not distracted by the selection of one particular coloring. For instance, if the first coloring choice is shown, with the DP separator error between the two blue polygons, the designer may be led to think that increasing the spacing between those two polygons is the correct debug solution. Actually, increasing any of the three spaces separating these three polygons is an equally valid solution, and will fix the odd cycle error. It may be that, due to other layout limitations, the spacing between the two blue polygons is the most difficult to increase, so the designer would end up spending excessive time focused on a less-productive solution. While there are reasons that fixing one particular spacing in an odd cycle error may be more beneficial than another, just seeing colors and separator errors does not make this evident. The idea of the RING is to show the designer the multiple fixing alternatives without implying a particular solution.

Another example of a DP error where seeing colors is not particularly helpful is when an odd cycle error shares a separator error with an adjoining even cycle. Fixing that particular spacing will actually create a new DP error involving the polygon(s) in the even cycle. If the designer were focused solely on the coloring of the odd cycle error, that outcome might be missed, and another round of debugging would be needed. In the Calibre Double Patterning tool, we identify these types of issues using a second ring, called a warning ring, as shown in Figure 2.

Figure 2: Example warning ring output to highlight preferred, less optimal, or unfeasible fix locations.

The orange warning rings in the right diagram identify the adjacent even cycles that will become part of a new error if the designer fixes the separator spacing where the red conflict cycle and the orange warning cycle touch. Additionally, modifying the shape of the red conflict rings helps identify separator locations where a spacing change can fix more than one error. While this obviously will greatly improve debug efficiency, none of this information is obvious from seeing the color output. It is the error and warning rings that provide the necessary input.

The third situation where a designer may to want to know the colors is when there is concern over parametric variability caused by the misalignment between the two masks. Because the single layer will be decomposed by the fab into two separate masks, and each of these masks will be patterned and etched separately during the manufacturing process, neighboring shapes in the layout may change relative spacing to each other from wafer to wafer, due to lithographic misalignment.

Because of this spacing change, the capacitive coupling between adjacent shapes can vary more if they are on opposite masks, rather than the same mask. There are some particularly critical or sensitive circuits, where understanding and potentially controlling this extra source of variation may be important to the designer, including:

• Matching between memory cells
• Sensitive analog circuits
• Differential circuits
• Analog instantiated in digital
• Matching between CPU cores

Figure 3 illustrates the various types of spacing changes and the corresponding effect on capacitive coupling that can occur.

Figure 3: Possible spacing changes and capacitive coupling impact caused by DP mask misalignment.

If the designer is concerned about a specific net and the variability of capacitive coupling to neighboring nets, then knowing the colors of those neighboring shapes may be useful. Of course, any shapes that are closer than the required color spacing to each other (shown by the separator between them) must be opposite colors. But any shapes whose common space is greater than or equal to same mask spacing requirements can be arbitrarily colored. Figure 4 shows an example of these spacing conditions.

Figure 4: Example coloring options around a polygon from a critical net.

In the original layer, the polygons labeled B and C are close enough to the critical net polygon that they must be the opposite color of the critical net polygon. Because of this, these polygons will have the maximum alignment variability. Knowing this, the designer may wish to move these polygons farther away from the critical net polygon so they can be arbitrarily colored relative to the critical net polygon, like polygons A and D. Given the original layout, the other three diagrams show some of the possible legal colorings. In the first coloring option, the two arbitrary colorable polygons A and D are the same color as the critical net polygon, so they would not misalign relative to the critical net polygon. However, in the second option, they happen to be the opposite color, and would misalign relative to the critical net polygon. In the third option, one is the same color and the other is the opposite, yielding a misalignment variation somewhere in the middle.

So, the critical question would seem to be, which one of these colorings will be the one the foundry generates when it create the masks? Sadly (for the designer), the answer is…there is no way to know. All of these coloring options are equally legal according to the design rules. Most designers believe that if they run the same script that their foundry uses to decompose the masks on their designs, they can expect to see the same colors the foundry will generate.

However, this is not so, and here’s why…All EDA DP decomposition tools use a form of graph processing to find a legal coloring. This technique is very sensitive to the slightest changes in the data that is presented to it, and may vary from run to run, or time to time, for any number of reasons. For example:

• Release-to-release changes in the tool algorithms;
• Changes in initial database construction, which can be affected by running in different configuration modes (e.g., flat, multi-threading, etc.);
• Running on a different number of CPUs;
• Other checks being executed in the deck during that run;
• Any changes to the layout, which will most likely cause different color selections to be made;
• Adding or removing a polygon anywhere in the layout;
• Moving any polygon or edge of any polygon;
• Adding or removing a cell or cell placement;
• Moving a cell to a different hierarchy, and
• Running the decomposition on the cell by itself, which will most likely yield different coloring than when decomposition is run on a cell placed in a larger cell or chip.

Remember, there is no inherent “meaning” in the particular colors shown in these options. They are all equally correct, so there is no intrinsic forcing function that causes the tool to always produce a particular coloring. This behavior is equally true for any vendor decomposition and checking tool, as it is integral to the graphing algorithm techniques by which all DP tools perform decomposition.

On the other hand, don’t get too anxious about this situation, for two reasons. First, the extraction corners provided by the foundry assume worst case, so if a layout passes the timing analysis, the circuit will work, regardless of which coloring happens to occur. Second, the designer does have some ability to control coloring for these special case critical circuits, or at least make sure certain polygons have matched coloring. To enable this control, most foundries provide an alternate DP flow in which the designer is allowed to “anchor” shapes to particular masks.

With anchoring, the designer is allowed to draw markers on important polygons to designate that they should be assigned a certain coloring. The automated decomposition tool recognizes these markers, and will always color those particular polygons those particular colors. For flows in which the designer does not decompose the design layers into two colors before tapeout, anchoring is the only way to be sure that certain polygons will be on certain masks. Figure 5 shows an example of a cell auto-decomposed with and without anchors. Notice that, in the anchored layout, the corresponding polygons in the decomposed layout match the color of the anchors as desired, and that these colors are different than the colors that were produced on the non-anchored version.

Figure 5: Example decomposition without and with anchor markers.

Using anchors guarantees designers that they will get the colors they want for the anchored polygons, but as seen in the example, it is possible to request coloring that will introduce coloring path violations between anchors, as indicated by the brown lines. The designer must still provide legal coloring solutions, even when using anchors.

So, if you have found yourself wanting to see colors during your DP design, first ask yourself, what is my motivation? Then use this article to help you decide if “color vision” is really something you need, or if “color blindness” is, in this case, actually a benefit.

—David Abercrombie is the advanced physical verification methodology program manager at Mentor Graphics.

Figure 1. The iterations between error fixing and signoff analysis are very challenging at advanced nodes.

This traditional approach to achieving design closure simply cannot meet the demands of the newest designs in terms of time-to-market and manufacturability. Rather than one iteration between signoff analysis and fixing, designers now face multiple iterations that may never converge. One of the key sources of difficulty is that the router technology files during layout in advanced-node designs are less complete and less precise than the golden signoff deck. As a new process node matures, the foundry’s design rules files—the SVRF decks—are continuously being updated to address manufacturing issues as they are discovered. The router’s technology files lag behind the SVRF, and are even unable to capture the complexity of some rules.

Hence, you have a DRC-clean design coming out of place and route that, when run through signoff analysis, actually has many violations. As you fix those violations, though, you may create new ones that won’t be detected until the design is again analyzed with the SVRF deck. There is no way to bridge this gap—you simply have to iterate between fixing and signoff analysis until you are satisfied with that the design will manufacture as expected.

From my point of view, the solution to the design closure challenges must come from EDA technology that combines the separate analyze-then-fix steps into one analysis-driven fixing flow. Perhaps the most important aspect of a flow that will analyze and fix DRC/DFM violations correctly in one pass is the use of golden signoff SVRF deck for both analyzing and driving repairs. This is the only sure way to reduce the signoff iterations that cost time and money. How would a flow like this work? Designers would use any place and route environment they want, tape out as usual and perform signoff analysis. But then, rather than reading the DRC/DFM errors back into the design environment—where the same router that couldn’t find the problems in the first place is tasked with fixing them—you would use the SVRF analysis to drive the fixes, thus insuring physical closure in that single pass.

The primary benefit of a tighter integration between analysis and fixing is a vast reduction in turn-around time by eliminating the multiple iterations needed now to reach closure. The design would be guaranteed DRC clean and highly manufacturable by the golden signoff tool used by every foundry. It would have the added benefits of removing late-stage surprises that can sink a design schedule.

—Jean-Marie Brunet is the product marketing director for model-based DFM and Integration to Olympus at Mentor Graphics.

Litho-Etch-Litho-Etch (LELE) is the most common technique of double patterning used in 20nm technology. The LELE DP technique first separates dense layouts that cannot be printed with a single exposure into two lower-density layout masks. It then uses two separate exposure processes to form two coarser patterns, which are then combined/superimposed to form a single finer image on the actual wafer. Figure 1 illustrates a 20nm layout that could not be printed with a single exposure (Fig.1a), but was successfully printed by splitting the layout into two masks.

Figure 1. After an unsuccessful single exposure (1a), this 20nm layout was split into two masks (pink and yellow) to produce an acceptable final silicon image (1b).

The adoption of LELE DP processing affects many aspects of the design flow, including parasitics extraction and the signoff methodology. The unavoidable misalignment of the layout masks causes variations in coupling capacitances between the polygons that are on different masks, which in turn affects both the couplings and the total capacitances of the nets.

As shown in Figure 2, some segments that are on different masks get closer together, while other segments get further away from each other, all due to relative mask shift. These shifts increase and decrease the coupling capacitances respectively. Total capacitance also is affected, due to asymmetry in the layouts. Capacitance change impacts circuit performance (the crosstalk, delay, or other circuit parameters), and must be accounted for in-circuit analysis.

Figure 2. Changes in the distance between figures caused by manufacturing variation affect both coupling capacitance and total capacitance.

Errors introduced by DP depend on mask displacement amount. Impact on coupling capacitance can be large, even while it is smaller on total capacitance, due to the different impact on coupling capacitances at the opposite sides of the conductor segments. Figure 3 shows the impact of an 8nm mask misalignment on total capacitance (left) and coupling capacitances (right) of a 20nm design. Vertical axes represent the number of the capacitance components, while horizontal axes show the percentage error relative to a non-shifted mask case. Standard deviation in total capacitance case is 6.4%, while it is much larger for coupling capacitance (23.3%). It should be noted that an 8nm misalignment is larger than a consensus estimate, and was used to provide a worst-case example. Also, the mask overlay impact on circuit parasitics, and consequently circuit design parameters, is design-dependent.

Figure 3. Error (by percentage), relative to non-shifted masks, introduced to total capacitance and coupling capacitance by a mask overlay of 8nm.

For a 6nm displacement, an error of about 17% on coupling and 6.5% on total capacitances was observed using typical test structures for evaluation. The error for a 2nm shift is, as expected, much smaller, in the range of 5% for coupling capacitances and about 2% for total capacitance.

Extraction approaches
The foundries and the EDA companies are striving to estimate the electrical impact of double patterning, and to develop extraction techniques that effectively and accurately analyze these DP effects. The dilemma is the tradeoff between simplicity (extraction methodology and analysis flow) and accuracy (analysis of the impact of DP on the performance parameters). The approaches, accordingly, can be classified into extraction-based techniques and analysis-based techniques. In extraction-based techniques, the goal is preservation of the existing extraction and analysis flow by using the common corners-based extraction approach, while the analysis-based technique shifts the burden to the analysis phase by extracting the netlists with sensitivities to spacing between the polygons, then applying statistical analysis techniques.

It also must be noted that either colorless or colored layouts [1] can be used in the extraction process. Colored layouts enable less conservative extraction, resulting in improved performance of the designed circuit. Although layout coloring can be performed with EDA tools or scripts provided by foundries, not all foundries like the idea of designers coloring the layout, and methodologies to extract the parasitics based on the original non-colored layout are needed. In the case when full coloring by customers is not supported, some flexibility is provided to customers, in the sense that they can put markers (or anchors) on the polygons to determine the mask on which those polygons should be placed.

Extraction-based techniques
Extraction techniques developed at Mentor Graphics to handle the impact of double patterning are summarized in Figure 4.

Figure 4. Extraction techniques.

The simplest technique to quickly analyze the impact of DP on circuit performance is to scale the capacitances and resistances by an estimated fixed value. This technique was used at the very early stages of development, but is not accurate enough for any real chip analysis.

The technique currently used by all major foundries is based on the dielectric constant change. The foundries provide tables for the dielectric constant change as a function of polygon width and spacing to other polygons. The dielectric constant change should produce the same effect on coupling capacitance as would the decrease or increase of polygon spacing due to maximum mask misalignment. As a consequence, two new corners (DP max and DP min) are produced for each original foundry corner, resulting in a total of 15 corners for a typical five foundry corners variation handling approach.

However, this approach is too conservative, because it accounts for unrealistic cases in which both left and right neighbors of a given polygon move towards it or away from it at the same time. In addition, it is typically applied to colorless layouts, which also introduces conservatism, since the same dielectric constant change is applied to the same mask polygons, even though they do not shift relative to each other. To alleviate this issue, anchoring is introduced as a way to specify which polygons belong to the same mask, to ensure that the dielectric constant change is not applied to the pairs of polygons located on the same mask.
An alternative, less conservative, and more physical approach has been proposed by Mentor Graphics. In this approach, in addition to regular foundry corners, custom corners are used to account for the impact of spacing change between the polygons caused by mask misalignment. Unlike the dielectric constant change-based approach, the custom corner approach does not consider unrealistic cases, but rather, accounts for any desired number of actual/possible mask shifts. In this way, the coupling capacitance on one side of a polygon that is surrounded by polygons belonging to a different mask increases, but at the same time, it decreases on the other side of the polygon. This approach will be applied to colored layouts, further improving the accuracy of the extracted capacitance and estimation of DP impact on circuit design parameters.

Both of the above extraction-based approaches introduce additional corners to the original foundry corners, which increases both the conservatism in extraction and simulation time. The foundries are doing analysis in an attempt to reduce the number of additional DP-related corners, since not all the original foundry corners require two additional DP corners to account for the worst case DP effect. A reduction to 11 corners has been reported, but it is not certain how well the corners cover the variation space. A single netlist is typically generated for each corner, and an increased number of netlists has a significant impact on both the simulation time and the overall analysis effort. To reduce the number of netlists, clustering of corners can be performed and a single multi-valued netlist produced for each cluster, thus reducing the number of netlists.

The most accurate DP extraction technique requires a completely different approach, which we will call the simulation-based approach. A netlist with sensitivities to spacing is produced, and a statistical method (e.g., Monte Carlo Analysis for analog designs, or Statistical Static Timing Analysis for digital designs) is used to obtain the distribution of the design parameter(s) due to DP. Accuracy is achieved at the expense of introducing statistical analysis, and it is questionable as to how it would be received by the designers.

References
1 David Abercrombie. “Colorblind—Colorless versus Two-Color Double Patterning Design,” Semiconductor Manufacturing & Design, March 2012.
Some of the material for this article was derived from “Double Patterning: Challenges and Possible Solutions in Extraction and Signoff Methodology,” Dusan Petranovic, Jim Falbo, Nur-Kurt Karsilayan: TAU 2012, Taipei, Taiwan, January 2012.

—Dusan Petranovic is the interconnect modeling technologist in the Design-to-Silicon Division of Mentor Graphics. David Abercrombie is the Advanced Physical Verification Methodology Program Manager at Mentor Graphics.

But let’s back up and talk about what’s changed with DRC and DFM over the past few years. When designing in process nodes at 90nm or earlier, getting a design to tape-out meant making sure your design met all design constraints (performance, area, power, etc.) and was DRC-clean. While this can be a challenge, it’s nothing compared to what designers face starting at 40nm, 28nm, and below.

At these nodes, DRC-clean is no longer sufficient to guarantee good yield. Even designs that pass rule-based DRC can still have yield detracting issues—issues that lead to parametric performance variability and even functional failure. At the root of the problem is the fact that those nice rectilinear shapes on your drawn layout (whether drawn manually or created with automatic P&R tools) do not print to silicon exactly as they’ve been drawn. Depending on your layout patterns and their nearby structures, the actual geometries on silicon may exhibit pinching (open), bridging (short) or line-end pull-back (see Figure 1).

Figure 1. SEM images of pinching and bridging. LPC finds these problems and lets you fix them before tapeout. Litho checking is mandatory at TSMC for 40nm, 28nm and 20nm process nodes.

These problems can no longer be fully fixed by applying OPC on the manufacturing side. This is why major foundries now require IC designers to perform litho simulation and to fix all Level 1 hotspots in the design stage before tapeout. TSMC’s terminology for this is Litho Process Check, LPC.

The traditional way to do this is to purchase software licenses and run litho checking in-house. This approach has the familiar and obvious benefits of software ownership. Designers have full control over when and how frequently they run the checks. The design database doesn’t leave the company’s network. There is a tight loop between updating the design database and re-running verification.

But what if a design house has not yet set up their own LPC checking flow and need time to plan or budget for software and CPU resources? Or what if a company only has a few tapeouts a year? These users can benefit from the flexibility and convenience of outsourcing the LPC check. These are a few of the situations that led Mentor to offer DFM Analysis Services to perform the TSMC-required signoff LPC.

DFM Analysis Services offers an alternative option to software purchase by performing litho checking for the customer. The customer delivers the encrypted design database to a secure electronic drop box. Mentor Graphics then runs TSMC-certified signoff Calibre LFD in Mentor’s secure data center in Oregon. The DFM Service can also be useful to customers who already have Calibre LFD licenses but find themselves in a situation where their computing resources are fully utilized.

Irrespective of whether a customer uses DFM Services or runs LPC in-house on purchased software, designers should run litho checking early and often to identify problematic structures early and allow more time to make the necessary fixes. Identifying weak layout structures early also allows design learning to feed back into improving the design flow. This will help to improve design robustness and avoid any last minute surprises or re-spins.

—Joe Kwan is the product marketing manager for Calibre LFD and DFM Services at Mentor Graphics.

Just mention double patterning (DP) to designers, and you can see the fear in their eyes. There is real trepidation about what kind of monster DP design debugging will be. In this article, I hope to alleviate some of that trepidation by educating you on manual correction techniques, automated fixing hints, and automated fixing capabilities you can adopt to help you with DP error resolution.

Quick recap—as you’ll recall from my previous articles, there are two basic types of DP errors that a designer will face, odd cycle and anchor path violations:

• An odd cycle violation identifies a group of polygons spaced such that any neighboring polygons must have opposite colors, but because of the odd number of polygons in the cycle, this color alternation cannot be evenly divided by two colors.
• An anchor path violation indicates that the user has “anchored” (pre-colored) a pair of polygons in the layout to ensure they are placed on certain mask layers, but there is a series, or path, of interacting polygons between the two anchors that cannot be colored in alternating colors to align with the anchor masks.

Figure 1 shows a layout containing both types of errors. The two red conflict rings indicate two separate odd cycle violations. The dark purple anchor path indicates a color alternation violation between the anchored polygon at the top and the anchored polygon at the bottom of the cell.

Figure 1: Example layouts containing odd cycle and anchor path violations.

If you are trying to manually correct an odd cycle or anchor path violation, there is good news and bad news. The good news is that, unlike most traditional DRC errors, these DP errors usually have multiple solutions. Since both error types result from the interaction of multiple polygons simultaneously, fixing any single interaction in the set fixes the error. For instance, if an odd cycle contains three polygons with three spacing interactions, the designer only has to edit any single polygon or spacing to fix the entire set.

The bad news is that most designers’ attempts to fix a DP violation often result in a new DP violation. There are two scenarios in which this tends to happen, which I’ll call extrinsic and intrinsic.

Figure 2 demonstrates the extrinsic scenario, in which attempting to fix the polygons and spaces of a given error produces a new error involving new polygons and spacings that were not in the original error (hence the term “extrinsic”). The original error shows three polygons in the middle of the design that interact to create an odd cycle of three, as highlighted by the red arrows. There are other polygons that interact with these three polygons, but they do not participate in this original error. The illustrations below show various ways in which a designer might try to move one of the original three polygons. In all three examples, the move fixes the original error, but creates a new error involving some of the polygons that were not part of the original error.

In this situation, there are some manual techniques that help you avoid this result. Figure 3 demonstrates two such techniques, each with multiple fix options. The first technique, shown in the top row, is to move single edges of polygons instead of moving entire polygons. The second technique, shown in the bottom row, is to either remove or split a polygon to fix an error. Both correction techniques can dramatically reduce the possibility of introducing new interactions that may lead to new errors.

Figure 3: Example techniques that can be used when fixing an odd cycle to avoid creating new errors.

In the intrinsic error scenario, the new error generated involves the same polygons that were in the original error (hence the term “intrinsic”). Figure 4 illustrates two intrinsic error examples. The left example occurs when any two of the polygons involved in the error have more than one point of spacing interaction. When the designer attempts to fix the violation by increasing the space at one of the points of interaction, the error remains after the modification, because there is still another point of interaction between the same two polygons. Since these multiple points of interaction may not be readily visible in the editing window, the designer is unlikely to notice them until re-running the check after the fix, only to find the same error occurring. The right example shows an odd cycle error that shares one or more separators with a neighboring even cycle that is not part of the original error. However, if the designer tries to fix the odd cycle by increasing the space at one of the separator locations shared by the neighboring even cycle, then a new error occurs that includes all the original polygons plus the polygons that were part of the even cycle.

Figure 4: Example of new “intrinsic” errors that can occur when trying to fix an odd cycle.

For intrinsic errors, automated fix hints can help you avoid creating new errors. Mentor Graphics has patented a new type of warning output that, combined with a slightly modified conflict output, greatly enhances the information available to designers trying to fix these types of issues. These new “warning rings” are shown in Figure 5. The left picture shows three errors containing odd cycles of three, and one odd cycle of five, with the traditional conflict ring output for odd cycle violations. In this traditional error visualization, the designer might logically assume that any of the separator spacings indicated by the rings could be modified with equal chance of success in fixing the error.

However, the combination of modified conflict rings and warning rings shown in the right picture tells a very different story. Any separator location in which both a conflict ring and a warning ring exist between polygons indicates that any attempt to fix the conflict ring by increasing that space will create a new error that expands to include the warning ring. For instance, the upper left odd cycle of three has one of the separators blocked by a warning ring, which tells designers to focus their efforts on the other two separator spacings. In the lower left odd cycle of three, two of the three separators are blocked by warning rings, leaving only one viable fix option.

The other type of information that can be gleaned from this innovative automated fix hinting is demonstrated in the two odd cycle errors on the right. In this case, the two conflict rings that share a separator spacing can both be fixed simultaneously by increasing this space, saving the designer significant time and effort.

Figure 5: Comparison of errors highlighted using only conflict rings versus the same errors highlighted with conflict and warning rings to assist in debug.

The last fix option for odd cycle and anchor path DP violations is what all designers want—automated correction. If the foundry process allows polygons to be “cut” into pieces that are colored separately and then “stitched” together by overlapping them at the point where the two pieces meet, an automated fix solution is possible. A large majority of DP violations can be fixed using this method, and Mentor’s DP checking and decomposition tools can find and insert these stitch locations automatically. Figure 6 shows a layout as originally drawn (without stitches) that contains several odd cycle and anchor path violations, and the same layout after Calibre® Multi-Patterning has automatically introduced stitches. The stitch locations are highlighted by the blue circles. Stitching fixed the majority of the errors automatically, and in the one location that was not fixable, the introduction of a stitch removed one of the warning rings, opening up an additional opportunity for the designer to fix it manually.

Figure 6: Example automated odd cycle and anchor path violation fixing using stitches.

If the thought of dealing with DP-related odd cycle and anchor path violations still gives you nightmares, let me assure you that double patterning is not a monster in the closet. The manual techniques, automated hints, and automated fixing that I’ve described here will make your life much easier. You will find that, with a little practice and patience, along with the right techniques and tools, you’ll very quickly become proficient and productive in DP-based design.

Please let me know what you think about these techniques and tools. Also, let me know if you have any creative DP debugging techniques or ideas of your own to share. Next time, we’ll look at how to deal with the parasitic variability impacts of DP-based design.

Author:
David Abercrombie is the Advanced Physical Verification Methodology Program Manager at Mentor Graphics. For the last few years, he has been driving development of EDA tools that can solve the issues in design to process interactions (DFM) that create ever-increasing yield problems. David received his BSEE from Clemson University, and his MSEE from North Carolina State University. He loves to play the guitar, explore the great outdoors, and watch a great science fiction show, but not all at the same time.