Before coloring your DP design you need to understand the impact of that decision.

Among the many steps involved with chip design, there is one known by the deceptively simple name of “fill”.

The challenges of double pattering (DP)-based design are looming large to those customers starting to move to the 20 nm technology node.

DFM is not something separate and apart from design rule checking (DRC).

Family histories are all the rage these days. With the advent of online databases, what was once a difficult and expensive task is now accessible to anyone with Internet access. Not only can you investigate census data, immigration records, and military service records with ease, but some sites also allow you to access information compiled by other site members. All of a sudden, finding out about your great-great grandparents is just a click away. The information hasn’t changed, but the methods of compiling and accessing it have.

Every new technology node brings new process challenges that translate into design challenges. For the last five years, design rules and processes have had to deal with an increasing impact from nearest-neighbor and environmental effects from lithography, stress, and temperature.

Given that my last couple of blogs on double patterning (DP) might have scared you to death, I figured it was time to bring you some good news.

A return on investment doesn’t happen until customers actually buy your product, so the most fundamental goal for designers is getting their designs to market.

Share and share alike! Our mothers always said it was the right thing to do, and it seems that this ideology is now coming front and center for double patterning at 20nm and below.

The need for tool Integration and the reality of competition create a Jekyll and Hyde dichotomy for the EDA industry