A New World For Fill At N20
By Jeff Wilson and Jean-Marie Brunet
There are many drastic changes required to design, verify, and manufacture semiconductors at the 20nm process node (N20). One of these is fill. At previous design nodes, fill was used just to ensure manufacturability by giving each layer (metal, poly, diffusion) an accepted density. At N20, fill is used to address many more manufacturing issues, and has become highly complex (Fig 1).
Two primary new concepts of fill at 20nm, particularly for SoCs, are 1) it must be process-accurate, and 2) it requires a hierarchical methodology.
Fill affects numerous aspects of manufacturability. Fill must be correct-by-construction, meaning the fill engine and analysis engines are integrated. It must comply with double patterning rules, forbidden pitch requirements, use cell-based process-validated fill patterns, and be timing-aware. Given the tight manufacturing constraints, fill for back-end layers and for front-end layers must be done by a foundry-certified fill utility, which requires both the fill rules deck and the fill software programs designed for the N20 process. There is no way around this fact. The foundries expect your GDSII to be filled with their foundry-certified fill utility, which have been developed in lock step with the manufacturing process.
Given the new complexity and importance of fill, the foundries want to make fill easier for you. Take double patterning: For fill layers, double patterning reduces manufacturing variability by balancing the light emitted through the mask, and leveling the impact of etch on the design. The foundry-certified fill deck and software makes double-patterning decomposition transparent. The complexity of fill is hidden—from the number of new rules required, to the merged fill/analyze processes—to reduce the impact of fill on the entire design team.
Change in fill methodology
One impact that the foundry-certified fill utilities can’t hide from you involves the changes to fill methodology that are needed for SoCs at N20. In the past, fill was added at the time of chip assembly, and then to the entire layout at once. Place and route tools usually added some fill to blocks before the SoC was assembled, but that fill acted as a sort of placeholder to help estimate density and timing/power impacts. It typically was stripped out so the more accurate fill could be added during the final full-chip verification and signoff steps.
This flat flow, in which fill was added to the top-level design, is a thing of the past. Why? Because of the growing design sizes. For N20, we expect design sizes of 100 billion to 200 billion transistors, and we expect to use much more fill to meet the manufacturing requirements. Consider this: For large SoCs at N20, the design size after fill is on the order of 5x the pre-fill design size. That’s a lot of fill. The only way to handle that much data is to first complete the fill for each block in the design before attempting top-level fill.
This hierarchical flow, with block-level fill done before top-level fill, is the only solution for managing file-size and run-time. In a hierarchical flow, top-level fill is for intra-block areas, and to touch up block-level fill once the blocks are considered in the top-level context. Mentor’s fill technology, called SmartFill, addresses all fill constraints—not just the basic minimum and maximum density constraints, but also the more advanced gradient (density difference in adjacent windows) and magnitude (density difference in windows across the design) constraints. SmartFill also balances the need to satisfy the constraints while minimizing the amount of areas with no fill with the smallest parasitic impact. SmartFill is able to achieve this balance and minimize the timing impact by reading a list of your critical nets so it avoids interfering with their performance by adjusting the spacing of fill shapes around these nets in both the lateral and vertical directions.
As a final note on fill methodology, your fill solution should integrate easily into your existing design flow. SmartFill, for example, is a Calibre product, so it plugs right into any existing Calibre flow. It also can read and write to multiple design databases (such as LEF/DEF, Open Access, and Milkyway), which ensures your fill flow will work with any major design implementation flow. The read capability allows the filling engine to make informed fill placement decisions (based on both the type of signals and which are timing-critical), while the write capability enables you to verify the design with fill in your signoff timing flow.
—Jean-Marie Brunet is the Product Marketing Director for Litho Friendly Design (LFD) and Design-for-Manufacturing (DFM) Products at Mentor Graphics Corporation.
—Jeff Wilson is a DFM Product Marketing Manager in Mentor Graphics’ Calibre organization.