Anchors Away – Anchoring and Seeding in Double Pattern Design.
Many aspects of how double patterning (DP) affects the designer depend on the methodology used and the level of control the designer wants. One extreme in methodology and control is full two-layer design, in which the designer decomposes the entire design and tapes out two masks. The designer has complete control of the coloring, but all the responsibility and work as well. The opposite extreme is colorless design, in which the designer draws a single layer for the whole design, only checking that decomposition is possible after tape out. In this methodology, the designer has no control over the coloring, but also avoids much of the work.
More typically, however, we see companies using and foundries supporting a methodology somewhere in between these two extremes. Using a mixed decomposition flow, the designer assumes control over the coloring of some portion of the design, and leaves the rest to the foundry. There are several reasons why this methodology has gained popularity:
- Decomposing an entire design, either manually or with automated assistance, adds significant effort and data size during the design process.
- The parasitic impact of misalignments associated with LELE double patterning in most of the design (particularly the digital portion) can be sufficiently accounted for without specific coloring information.
- Only very critical circuits, nets, or cells require control of the coloring to reduce potential randomness in variability that could occur if the foundry arbitrarily colored them.
- The un-colored portion of the layout leaves the foundry with some flexibility to tweak colors if needed to address any manufacturing issues.
An example of a critical circuit for which the designer may want to control at least some of the coloring would be a matched analog circuit. Assume that the circuit contains a set of four shapes that are spaced slightly larger than the minimum same color space so that they can be arbitrarily colored. If these shapes must be mirrored in the matched circuit, the designer does not want one set of shapes to be colored blue, green, blue, green and the mirrored set to be colored blue, blue, blue, blue, as the parasitic variability in the first set would be much higher than the variability in the second set if mask misalignment occurs, thus mismatching the circuit performance. In cases like this, there must be some way to control the coloring of part of the layout, while ensuring the uncolored portion has at least one valid coloring solution for the foundry to apply after tape out.
Figure 1 illustrates the methods used today by foundries and EDA tools to address this need. As shown in the default column example, the four shapes as drawn in a single layer have two possible valid coloring options. Using a methodology called anchoring, the designer is allowed to overlay a marker layer onto one or more of the single layer shapes that tells the DP decomposition and checking tool that the shape should be assigned to a particular mask. This anchor then influences the allowed coloring of neighboring shapes that are within a separator distance, reducing the valid coloring solutions in our example from two to one. A similar, but slightly different, version of this is called seeding, in which the designer also draws a marker layer to specify the mask color to be applied, but the marker does not cover the entire original polygon. This “seed” marker sets the coloring for the rest of that shape, similar to the anchor approach.
Figure 2 shows how these techniques may look in a more realistic design layout. In the example cell, the power and ground busses are each seeded to be on mask0, and a few of the internal cell shapes are either anchored or seeded to one of the two masks. The resulting output of the DP decomposition tool shows how these anchors and seeds were followed, and the remaining design shapes were colored accordingly.
The distinction between anchoring and seeding seems relatively trivial until you look at a double patterning process that allows stitching. Figure 3 shows a simple layout example of two shapes in which various anchor or seed markers are applied. The two input shapes are separated such that they must be opposite color.
In the first two examples, where a single anchor or seed marker is used on a single polygon, the resulting output is obvious and the difference between the two seems trivial. However, examples 3-6 show the differences that seeding may introduce.
In example 3, two different seeds are applied to the same polygon. In a process that does not allow stitching, this would be an invalid application. As a result, processes that do not allow stitching typically only allow anchoring (i.e., the marker must completely cover the original polygon).
If the process allows stitching, example 4 shows how the DP decomposition tool inserts a stitch to resolve the difference in color markers on the same polygon. The location of the stitch will be at some arbitrary point along the polygon, unless the designer actually forms the desired stitch by overlapping the two seed markers (as shown in example 5).
Example 6 demonstrates that, even with stitching, the designer must be careful not to draw multiple markers on the same shape that would lead to an improperly formed stitch. The DP decomposition tools assume that any user-drawn color (seed or anchor marker shape) cannot be modified, so in this example, the lack of overlap is not auto-corrected, as it would change the original marker definition, and the result causes DRC violations against rules for proper stitches.
Of course, there are other types of errors associated with the application of anchor or seed shapes that make a design invalid for DP decomposition. If two polygons are anchored to a particular mask, and there is some string of uncolored polygons connecting them that are all spaced such that they require the colors to alternate, then it is possible that the anchors assigned by the designer cannot be followed while also honoring the color alternation indicated by the separators. In Figure 4, the leftmost polygon is anchored to mask0 and the rightmost polygon is anchored to mask1. However, because of the separators connecting the series of polygons between them, the blue anchor on the left would ultimately require the rightmost polygon to also be blue. However, the designer has anchored this polygon green, so a valid coloring solution does not exist. The DP checking tool has several ways to indicate this type of error, and two are shown here. The first is to output all the polygons in the “chain” between the two anchors. The second is to produce a line that connects the two anchors across the polygons in between.
Figure 5 shows a layout that contains both traditional odd cycle errors and path errors caused by seeds. In this example, you can see that a given polygon may participate in one or both of these types of errors simultaneously. Just like an odd cycle error, the designer uses the same basic techniques to fix an anchor path violation—one of the spaces along the path must be increased to allow two neighboring shapes to legally be the same color, or a polygon must be removed to break the path. In the path error on the right, you can see that two of the separators are shared by the path violation as well as the odd cycle violation, so increasing one of these spaces would fix both simultaneously. In addition to these fixing methods, the designer could also change the color of the anchor at one end to fix the path.
Anchoring and seeding enable a nice tradeoff between providing designers control of coloring where they need it, and ensuring manufacturing flexibility to arbitrarily color the rest of the layout as desired. However, this capability also introduces the potential for new types of DRC violations that must be addressed by the designer before taping out the design to the fab.
Have you already discussed which options for coloring control will be supported by your foundry? Have you tried using anchors or seeds in your designs? Let me know in your comments to this blog. In my next blog, I will look at triple patterning, which is likely to become a new requirement at 14nm.
David Abercrombie is the Advanced Physical Verification Methodology Program Manager at Mentor Graphics. For the last few years, he has been driving development of EDA tools that can solve the issues in design to process interactions (DFM) that create ever-increasing yield problems. David received his BSEE from Clemson University, and his MSEE from North Carolina State University. He loves to play the guitar, explore the great outdoors, and watch a great science fiction show, but not all at the same time.