Fill Challenge Solved: Why SmartFill is as Good as it Sounds
by Jean-Marie Brunet
Among the many steps involved with chip design, there is one known by the deceptively simple name of “fill.” Fill involves adding shapes or polygons to the design that are structural, not logical. That is, they ensure manufacturability by making sure each layer (metal, poly, diffusion) has a proscribed density. As easy as this sounds, fill can be tricky, and the fill technology a chipmaker uses can impact design parameters like timing, design schedule, and ultimately cost.
In the olden days, the only option for metal fill was something we call “dummy” fill. The shapes were added somewhat blindly with a software program, then the design was streamed out in GDS format and analyzed for DRC and perhaps timing. These days, given the complex nature of advanced node designs, the software program must be aware of all the impacts the fill might have on a design. That is, the fill must be “smart,” meaning it integrates an analysis engine with the filling algorithm and performs analysis concurrently with fill insertion; a technique that qualifies as correct-by-construction. The result is minimum fill, complete adherence to constraints, improved manufacturability, and a faster run time.
Let’s look at an example of the impact of using smart fill in a joint project by ST–Ericsson and STMicroelectronics. The designers used Mentor’s SmartFill solution (part of the Calibre YieldEnhancer product) to ensure they not only met their design parameters, but also the time to market constraints for their U8500 Smartphone platform. ST-Ericsson used an aggressive set of fill-related rules to minimize the impact of manufacturing variables. Their standard dummy fill rule deck occasionally failed to meet all density-related constraints. In particular, an earlier release of the U8500 design failed to reach its density-clean goal because of two design rules. ST-Ericsson concluded that dummy fill could not correctly fill such a complex design, so they tried the SmartFill technology.
The table below shows the improvement in the DFM score ST-Ericsson obtained by using the integrated filling solution, while also saving a week in the production schedule.
Table 1 – Improvements obtained by ST-Ericsson using Calibre SmartFill processing
Because the U8500 design is leading-edge, it was critical for ST-Ericsson to ensure that timing constraints were met and that the design would perform at specification. Timing is related to both resistance and capacitance. Resistance is affected by the thickness of the metal, which is determined by planarity of the design and depth of the trench. Capacitance is related both to the space between the interconnects and their neighboring metal fill shapes. This is why dummy fill won’t work; it can’t balance the density constraints against the reduction in the amount of capacitance added to the design. The SmartFill process addresses all fill constraints; not just the basic minimum and maximum density constraints, but the more advanced gradient (density difference in adjacent windows) and magnitude (density difference in windows across the design) constraints. The key element is to satisfy the density constraints and other rules with the smallest parasitic impact. SmartFill is also able to read a list of your critical nets, and then avoid interfering with their performance by using more spacing.
Not only did SmartFill create DRC-clean fill in less time, but it helped with manufacturability. SmartFill lowered the impact of optical proximity correction (OPC) by improving the depth of focus measurement (i.e., the planarity) and reducing the number of fill shapes (by 90% in the ST-Ericsson design). These improvements saved money by reducing OPC processing time, and by giving the OPC engine more room with which to work. ST-Ericsson also used SmartFill to place test structures before the general fill process, a step that is very challenging for dummy fill flows. Using SmartFill allows the layout information of the test structures (like density) to be considered before the fill is added.
There are many things in life and chip design that you can’t control, but fill isn’t one of them. ST-Ericsson saw enough benefit from SmartFill on their 45 nm U8500 design that they plan to use it as their only fill solution at 32 nm. To read more about the ST-Ericsson and STMicroeletronics case study, download the whitepaper.
You can also learn more about fill challenges at advanced nodes at the SPIE Advanced Lithography conference in San Jose, CA. Here’s a link to the program. Go see the session titled “The complexity of fill at 28nm and beyond,” at 2pm on Thursday, February 16, 2012, in which Mentor and AMD engineers explain the effects of fill layout through the entire semiconductor manufacturing system, from mask generation to final test. They will also discuss enhancements to the current EDA fill tool technology and methodology to address these issues. You’ll find more and more design side content at the lithography conferences these days, a clear indication of the importance of design and verification issues, like fill, to manufacturability at advanced nodes.
Jean-Marie Brunet is the Product Marketing Director for Litho Friendly Design (LFD) and Design-for-Manufacturing (DFM) Products at Mentor Graphics Corporation. He holds a Master’s degree in Electrical Engineering from I.S.E.N Electronic Engineering School in Lille, France. Jean-Marie Brunet can be reached at firstname.lastname@example.org