A Smart Filling Solution Yields Multiple Benefits
By Jeff Wilson, Mentor Graphics
A return on investment doesn’t happen until customers actually buy your product, so the most fundamental goal for designers is getting their designs to market. While there are numerous steps along the way, one task that must be performed is adding fill to the design. Fill is like design rule checking (DRC)—it’s not an optional step, because it is needed to ensure the manufacturability of the design. Regardless of the fill technique used (e.g., bottom-up, top-down), a final fill process must be run following the final assembly, and one last verification must be run on the design with fill to ensure the design passes all density checks. Because fill is mandatory, it is critical to find a solution that can complete these tasks in as little time as possible, while providing the best possible fill configuration for your design. Overall fill time is impacted by a number of factors, including run time for adding the fill, and analysis time to ensure that fill passes all DRC checks and that the impact on other aspects of the design (e.g., timing) is minimized.
The time required for fill is increasing because of growing design sizes, as well as the complexity of today’s filling process. Fill is no longer limited to improving just the planarity of the design, so there are a growing number of fill-related rules that need to be monitored and satisfied to have first pass success. As the technology continues to advance to smaller features sizes, the types and extent of fill analysis continue to increase. What were once mainly DRC density checks focused on minimum and maximum constraints have now expanded to include density gradient (differences between adjacent windows) and density magnitude (differences across the entire chip). In addition, customers are adding even more constraints, such as perimeter and uniformity of fill spanning multiple layers, to the growing number of DRC checks. To have a correct by construction flow, the fill solution needs to incorporate a robust geometric processing engine that can handle all these layout constraints concurrently.
ST-Ericsson and STMicroelectronics discussed some of these new manufacturing rules, and how they used advanced fill technology to ensure they not only met their design parameters, but also their time to market constraints, for their U8500 Smartphone platform in a recent
white paper. To produce a DRC-clean design that also significantly improved the design’s DFM score, ST-Ericsson chose a solution that integrates an analysis engine with the filling algorithm. Significantly, their fill solution (Calibre YieldEnhancer with SmartFill technology) is based on the same platform that is used for their final DRC signoff, ensuring that fill will not introduce signoff violations late in the design flow. This fill solution addresses all spacing and density checks, such as min/max, gradient and magnitude. The table below shows the improvement in the DFM score ST-Ericsson obtained by using the integrated filling solution, while also saving a week in the production schedule.
Of course, DRC-clean is the top priority, but right on its heels is making sure that timing constraints are achieved. In the past, good planarity could be achieved without much impact on performance (timing) by simply filling in unused areas of the layout to achieve a metal density target. But advanced node ICs require explicit analysis during the filling process to balance density constraints against the amount of capacitance added to the design. This required balancing act puts additional pressure on an analysis-driven solution to add fill in the correct amount and location. Using a filling solution that can read and write to multiple design databases (such as LEF/DEF, Open Access, and Milkyway) provides confidence to customers that they have a filling flow independent of which tools they use to implement their designs. The read capability allows the filling engine to make informed fill placement decisions (based on both the type of signals and which are timing-critical), while the write capability enables customers to verify their design with fill in their signoff timing flow.
Designers can’t control all aspects required to achieve a positive ROI, but what they can control, they need to do as well as possible. This includes producing a filled, DRC-clean design that optimizes the use of physical space and meets timing constraints, all in the shortest possible time. A correct by construction fill solution combines sophisticated filling algorithms with DRC analysis and timing-aware placement to produce first-pass success.
Jeff Wilson is a DFM Product Marketing Manager in Mentor Graphics’ Calibre organization. He is responsible for the development of products that address the challenges of CMP and CAA. He previously worked at Motorola and SCS. Jeff received a BS in Design Engineering from Brigham Young University and an MBA from the University of Oregon.