Litho Community Meets And Votes
By Marc David Levenson
Every 18 months or so, the leading lithography lights of the IEEE meet in an off-the-record workshop to discuss the state and future of our craft. This year’s event took place amid the restored colonial splendor of Williamsburg Virginia in June. Co-chairs Mordechai Rothschild and Lars Liebmann assembled a technical program that covered not only lithography for semiconductor manufacturing, but also the larger technical and economic context.
Attendees heard of the steady progress of EUV lithography towards an ever-receding HVM insertion window, the yet-to-be-fulfilled potential of multi-beam electron lithography, the various flavors of 193nm immersion lithography extensions with deposition and self assembly, etc. But they also heard about graphene and nanotube circuit elements, design options, 3D chips and NEMS relay gates for really low power consumption.
At the end of the presentations and debate, the attendees were asked to put themselves in the position of the R&D director of a company that relied on the fabrication of leading edge devices. How would limited funds be invested? Each attendee was given $100 in fake money to apply to near-term development of 25nm technology for 2014 and another $100 to apply longer term, for 13nm equivalent in 2020. How would the money be spent?
In the short term, 41.2% of the funding went toward multiple exposure 193nm immersion lithography either using self aligned spacers and cut mask exposures or litho-etch litho-etch. Second choice was 3-D integration, with 18.1% of the funding. EUVL came in fourth, after e-beam lithography. So, participants seemed to believe that methods that work now would reward investment for another two years.
Longer term, the top contenders were more evenly funded. E-beam direct write narrowly edged out directed self assembly 26.4% to 25%, while EUVL came in third with 18.6% (http://www.lithoworkshop.org/investment-results/). If the real-world R&D funding mimicked the preferences of the workshop experts, the technology world would be different! How fast might progress be if EUVL received only 18% of Sematech’s litho budget and the rest was spent on other technologies?
The skepticism expressed on EUVL perhaps resulted from the numerous issues raised openly by workshop participants who knew they could not be quoted directly. To be sure, Jos Benchop of ASML had progress to report with all six pre-production EUVL tools shipped and the first NXE/3300B HVM scanner with 0.33NA optics having printed its first wafer. However, the EUVL program was far enough along that true operational difficulties could be glimpsed.
Yan Borodovsky of Intel summarized some concerns he expressed in his presentation at the recent EUVL meeting in Maui (www.euvlitho.com/2012/p1.pdf). Borodovsky had explored using EUVL for the difficult “cut-mask” step of Intel’s “line-and-cut” complementary lithography paradigm for HVM at 14nm. He found that reducing the stochastic edge placement error of positive tone EUV resist for 20nm contact-like features to about 3nm required low sensitivity resist and a 1000W EUV power level at the intermediate focus—an order of magnitude larger than current targets. Moreover, the 3D EMF effects at the mask would give rise to different image distortions at different locations along the exposure slit, requiring extensive OPC for proper patterning. A yet-to-be-developed fast and accurate approximation method would be required to validate full chip OPC schemes. Other speakers also worried about the mask, especially the phase roughness of the multi-layer reflector. In focus, those fluctuations may have little impact, but just 50nm out of best focus; they produce a “sea of defects” with 10% random CD error on 22nm dark lines. At larger NAs the challenge seemed even worse.
In contrast the prospects for 3D stacking with through-silicon vias seemed more promising. Today’s “3D” chip production is mostly “2.5D” silicon interposer technology, but relevant tools are being exercised and widespread true 3D awaits better design tools and standards, according to one speaker. Another predicted that design and process flexibility would lower the NRE of modular chip stacks compared to today’s SoC paradigm. The needed 0.25-micron overlay accuracy has already been demonstrated with a full 8-inch wafer, low-temperature stacking method described by Jeremy Muldavin of MIT’s Lincoln Laboratory. The wafers are full thickness when stacked, but the substrate is removed after oxide-to-oxide bonding, leaving 15 microns of silicon. Lincoln Lab has assembled heterogeneous wafer types with 3 active layers. The stepping error of the fields on the wafer adds measurably to the overlay error!
Robert Patti of Tezzaron Semiconductor described his company’s progress in “dis-integrating” the logic and memory of a chip stack. In a DRAM stack, for example, the controller chip can be built using a logic process while the memory array chips can be built for low leakage. The net effect is tremendously improved power efficiency and higher yields. How can yields be higher in 3-D than 2? Well, DRAM is repairable using redundant strings of cells that can be switched in to replace defective ones. In 3-D, if you run out of spare strings on one layer, you can use those on another. According to Patti the repairability increases faster than the defectivity as layers increase!
Directed Self-Assembly Magic
Block co-polymer films can be persuaded to assemble themselves into seemingly useful patterns aligned to physical steps on a wafer (grapho-epitaxy) or chemical patterns on the surface (chemo-epitaxy). But what if the template is ambiguous, allowing more than one pattern to be formed?
Karl Berggren of MIT showed how a sparse square array of chemically coated posts can serve as a template for either vertically or horizontally oriented polymer stripes. If an occasional post is replaced by a closely spaced pair, the orientation of that pair can force the local line pattern to orient in that direction. Other judiciously placed pairs can cause the stripes to form L-bends, line ends and other patterns that resemble metal interconnect layers. The same imprinted post pattern (with minimal e-beam personalization) could then be used for many designs, if connection fidelity can be demonstrated.
Even if we can build semiconductor chips on 14, 10, 7 and 5nm ground rules, there must be a point where something new replaces CMOS. What might that be? Prof. Sanjay Banerjee of the University of Texas at Austin described the work of the Nanoelectronics Research Initiative on some options: “spintronics,” “orbitronics,” “phononics” and “pseudospintronics.” All are attempts to reduce energy consumption down towards the Landauer limit. Of these, the most remarkable seemed to be “pseudospintronics” which would employ a unique quantum property of bi-layer graphene for information processing.
In Banerjee’s proposed Bilayer pseudoSpin Field-Effect Transistor (BiSFET), holes and electrons would propagate on different graphene sheets separated by a thin insulator. When gated properly, the holes and electrons would bind into excitons and Bose-condense, dramatically increasing the tunneling current through the insulator thus switching the BiSFET on, all at room temperature! Such speculative ideas attracted fully 7% of the long-term investment in the final survey!
The 2012 lithography workshop occurred at an inflection point, when the manufacturing technologies as well as the market motivations are changing. Today, power consumption matters more than speed in consumer—and most commercial—applications. Super-fast, power-hungry chips may still be sold for the supercomputers that drive the high frequency stock trading that has proved so lucrative for some, but even the giant server farms of Google and Facebook now demand low cost and low power chips.
When long-delayed R&D programs fail to respond to such changes in the environment, even technological success can lead to commercial failure. Alternate schemes appear that fit the requirements of the changed environment. That was the lesson of the Concorde supersonic transport and the Space Shuttle, according to one speaker. Is the lithography community about to experience the collapse of our EUVL mega-project? We will know by the time of the next IEEE Lithography Workshop 18 months from now.