By David Lammers

For the second year in a row, July kicked off on a bit of a chilly note. Last year, executives talked about a “pause” in orders, and, sure enough, July 2011 began what proved to be a poor second half for the semiconductor industry.

This year, a similar story appears to be unfolding, as the otherwise lively Semicon West in San Francisco began with Applied Materials CEO Mike Splinter explaining that “a bit of seasonality” has crept into the industry. Applied’s strong order book for semiconductor equipment, he said, had weakened due to foundry pushouts.

Since then, non-foundry companies have been acting cautiously, with Toshiba cutting NAND production by 30 percent, for example, and Texas Instruments expressing concerns about its order book.

Gartner analyst Dean Freeman said the equipment order pushouts are largely due to a couple of large foundries “overinvesting” in recent quarters. TSMC usually adds about 20,000 wafer starts of leading-edge capacity in one year. This year it is on track to add 50-55k wspm – more than two years worth of new capacity in a single year. Delays in getting TSMC’s new fabs ready are contributing to the equipment order hiccup.

Samsung also is investing, bringing its total capacity add this year up by 65,000 wspm. With Apple due to unveil the iPhone 5 in October, perhaps, and Samsung’s smartphones selling very well, Samsung needs new capacity.

The short-term view must be balanced with a big picture outlook. It was just a couple of months ago that Qualcomm and others were screaming for more 28nm capacity. (Stock analysts use the word “lumpy” to describe foundry investments.)

Bob Johnson

Gartner is predicting that semiconductor industry capex will have a compound annual growth rate (CAGR) of only 0.6 percent between 2011 and 2016. Because 2011 was a fairly strong capex year, the number appears low, but if the time period is shifted to 2010-2016 the semiconductor capex CAGR improves to only 3 percent, said Gartner analyst Bob Johnson, speaking at the SEMI/Gartner market forecast event at Semicon West.

The main problem is the world economy. Instead of the 3.6 percent global GDP growth expected for this year, the world economy will be lucky to eke out 3 percent growth, a huge difference for the chip industry. And while the very largest companies are investing heavily, the much larger number of small- and medium-sized fab owners are investing relatively little.

Splinter looks at the world economy and sees various challenges, including “weaker economies in China and Europe than we saw last year. PC shipments are quite weak, and NAND shipments also are less than what we thought. And there are certain factory operational issues at some customers.”

None of this seemed to dampen the overall mood at Semicon West. Dan Hutcheson of VLSI Research said the activity level at West was among the highest ever. Bob Hollands, the head of U.S. marketing for ASM International, also was upbeat. “Sure, the world economy is shaky now, and there are some customer delays. When demand does pick up, they expect us to be able ship equipment to them quickly – they need it in five minutes.”

Dan Tracy, the SEMI market statistics director, was positive, though he may have tempered his optimism in the weeks since Semicon West. While semiconductor capex will decline slightly this year, Tracy sees a 10 percent gain next year, to $46.7 billion. Korea will be the largest market next year, followed by North America with $10 billion in capital investments, led by Intel’s build out of Fab 42 and D1X. And don’t ignore Japan: it is still at or near the top in terms of materials, with a large number of fabs consuming wafers, chemicals, and other materials.

Christian Dieseldorff

SEMI senior analyst Christian Dieseldorff said at this time last year SEMI was pessimistic about new fab construction. But there are now 26 construction plans underway for next year. TSMC is building four fabs at the same time. Samsung has a “superfab” underway at Line 16 in Korea, as well as the S1c and S1d expansions.

“Things are looking pretty rosy for this year, and we could see 2013 hit an all time record,” Dieseldorff said.

I think the world economy is too shaky to put a “rosy” label on the industry’s prospects. We all remember 2009 after Lehman Bros. went bankrupt and the U.S. housing bubble burst. The possibility of both Europe and China solving their financial issues soon is fairly remote (not to mention Japan’s energy crisis).

One of the great things about going to sunny and cool San Francisco for Semicon West is the chance to meet what we journalists call our “good sources.” I ran into Len Jelinek, the semiconductor manufacturing analyst at IHS iSuppli, and he brought the chip industry’s prospects down to ground level. “Just ask yourself,” Jelinek said, “when was the last time you bought a new laptop, or a new TV?” His point is that people are learning to make do with what they have.

His question brings to mind a quote attributed to the Greek philosopher Epicurus: “Nothing is enough for the man to whom enough is too little.”

By David Lammers

With Semicon West just a few weeks away in San Francisco, this is a good time to chew on some of the technical and business challenges facing the semiconductor industry, and ask yourself the question: Are you optimistic, or not?

I ask that question having read of young Ben Franklin, who was planning to open a print shop in colonial Philadelphia. His older acquaintance warned him not to do it, pointing out how many competing printers were struggling to survive, how the moral decay in Philadelphia had reached such alarming proportions, and so on. Franklin mused that his friend had the type of gloomy nature which expressed itself in a certain lack of faith in the future of his fellows, and of course Franklin plowed ahead with his business plan.

Which brings us to the question often mentioned in relation to EUV lithography: The “When/If” question. Asked whether EUV will “make it” in high-volume production, the EUV optimists argue that it is “Not a question of If, but When.” The non-optimists believe EUV will never be used in commercial production, partly for cost reasons, putting themselves in the “Not When, but If” camp.

I bounced the When/If question off of Franklin Kalk, the CTO of Toppan Photomasks, at a recent lunch here in Austin. A few weeks earlier, at the Advanced Semiconductor Manufacturing Conference in Saratoga Springs, New York,  Sematech lithography program manager, Stefan Wurm of GlobalFoundries, had suggested that masks, and specifically defect-free mask blanks, were a bigger challenge to EUV than the source power question.

Kalk said the DRAM makers need EUV, and will start using it as early as next year even if the throughput is limited to 30 wafers per hour. From that point, the source power vendors, such as Cymer, “probably can accelerate development.”

Kalk said he does have a lot of concerns about the mask blanks. With today’s masks, it is a matter of “find and fix” the defects. But with EUV, once a defect becomes embedded in the “superlattice” of multiple Mo-Si layers, the challenge becomes “changing the imaging characteristics of the defects rather than removing them.”

The lithography industry will really need EUV at the 14nm node, when the pitch will be in the 60nm range and as many as a dozen layers may require EUV, or failing that, double patterning.

What about e-beam? I asked. “E-beam is not going to happen, mainly because of the data throughput challenge. It might make sense for the military guys, because they only need one or two wafers. There aren’t that many F22’s made every year,” he noted, and E-beam could enhance the security of making those chips. But for volume manufacturing, E-beam direct write is too far behind.

What about imprint? Kalk said imprint will be increasingly challenged by the need to make a perfect reticle, with a 1X approach (i.e, the template patterns are the same size as the patterns on the wafer).

(Kalk and Wurm will be among the seven speakers at a lithography TechXPOT at Semicon West on July 11, starting at 10:30 a.m. in the South Hall. Earlier that morning, track vendor Sokudo will host its lithography breakfast, which this year will focus on directed self assembly.)

The Cost Question

After EUV, my biggest concern is the cost-per-function question. If we assume scaling will be doable, can we so easily assume it will be affordable? Will the 25 percent per-annum cost reduction trend continue? It is worrisome indeed to read that experts such as Handel Jones are predicting that the cost of making a transistor may actually go up soon.

There are other challenges, most of which are yield and cost related. Bringing in through silicon vias is a wonderful idea that will surely be adopted for the high-performance, high-priced solutions. But it will require innovation to keep yields high and costs low for commodity ICs with strict price windows.

How about the new transistor types? FinFETs are doable, but it may take awhile before the process flows are ironed out and yields reach acceptable levels. Perhaps a planar, fully depleted SOI approach could be less expensive for some vendors, providing the IP libraries can be more fully developed by the SOI camp.

How about the heterogeneous transistors, in which a germanium channel is deposited in the PFET and an InGaAs channel in the NFET? This approach uses a silicon wafer as the starting substrate, and requires deft deposition skills for the non-silicon channel materials used to boost mobilities in the critical circuits. In a sense, that path is already being trod by GlobalFoundries and others, which use a germanium-rich channel to boost hole mobilities at the 32/28nm generation. This subject will be taken up at Semicon West during a Tuesday TechXPOT, “Enabling Sub-22nm with New Materials and Processes” featuring Sematech’s Raj Jammy, Intel’s Kaizad Mistry, and Carlos Mazure of Soitec, among others.

450mm Wafer Transition

Semicon West is one of the best places to find out about the 450mm wafer transition.  The 450mm Supply Chain Forum will be held on Thursday morning, featuring Michael Liehr, general manager of the Global 450 Consortium at Albany, N.Y., Ron Rinfret, 450mm program director at Intel, and Kirk Hasserjian, a vice president at Applied Materials, among others.

Unfortunately for the industry, the EUV and 450mm wafer transition questions have become co-mingled. ASML has spent roughly $2 billion (€1.5 billion) in development of EUV, and it needs to recoup those investments with the 300mm EUV scanners it is bringing to market starting this year.

Which perhaps creates another If-When question, this time for 450mm: IF EUV arrives on 300mm tools, WHEN will 450mm wafers be widely adopted?

Even good-humored Ben Franklin, I’d wager, would have a tough time figuring that one.