To Semicon West, with Questions
By David Lammers
With Semicon West just a few weeks away in San Francisco, this is a good time to chew on some of the technical and business challenges facing the semiconductor industry, and ask yourself the question: Are you optimistic, or not?
I ask that question having read of young Ben Franklin, who was planning to open a print shop in colonial Philadelphia. His older acquaintance warned him not to do it, pointing out how many competing printers were struggling to survive, how the moral decay in Philadelphia had reached such alarming proportions, and so on. Franklin mused that his friend had the type of gloomy nature which expressed itself in a certain lack of faith in the future of his fellows, and of course Franklin plowed ahead with his business plan.
Which brings us to the question often mentioned in relation to EUV lithography: The “When/If” question. Asked whether EUV will “make it” in high-volume production, the EUV optimists argue that it is “Not a question of If, but When.” The non-optimists believe EUV will never be used in commercial production, partly for cost reasons, putting themselves in the “Not When, but If” camp.
I bounced the When/If question off of Franklin Kalk, the CTO of Toppan Photomasks, at a recent lunch here in Austin. A few weeks earlier, at the Advanced Semiconductor Manufacturing Conference in Saratoga Springs, New York, Sematech lithography program manager, Stefan Wurm of GlobalFoundries, had suggested that masks, and specifically defect-free mask blanks, were a bigger challenge to EUV than the source power question.
Kalk said the DRAM makers need EUV, and will start using it as early as next year even if the throughput is limited to 30 wafers per hour. From that point, the source power vendors, such as Cymer, “probably can accelerate development.”
Kalk said he does have a lot of concerns about the mask blanks. With today’s masks, it is a matter of “find and fix” the defects. But with EUV, once a defect becomes embedded in the “superlattice” of multiple Mo-Si layers, the challenge becomes “changing the imaging characteristics of the defects rather than removing them.”
The lithography industry will really need EUV at the 14nm node, when the pitch will be in the 60nm range and as many as a dozen layers may require EUV, or failing that, double patterning.
What about e-beam? I asked. “E-beam is not going to happen, mainly because of the data throughput challenge. It might make sense for the military guys, because they only need one or two wafers. There aren’t that many F22’s made every year,” he noted, and E-beam could enhance the security of making those chips. But for volume manufacturing, E-beam direct write is too far behind.
What about imprint? Kalk said imprint will be increasingly challenged by the need to make a perfect reticle, with a 1X approach (i.e, the template patterns are the same size as the patterns on the wafer).
(Kalk and Wurm will be among the seven speakers at a lithography TechXPOT at Semicon West on July 11, starting at 10:30 a.m. in the South Hall. Earlier that morning, track vendor Sokudo will host its lithography breakfast, which this year will focus on directed self assembly.)
The Cost Question
After EUV, my biggest concern is the cost-per-function question. If we assume scaling will be doable, can we so easily assume it will be affordable? Will the 25 percent per-annum cost reduction trend continue? It is worrisome indeed to read that experts such as Handel Jones are predicting that the cost of making a transistor may actually go up soon.
There are other challenges, most of which are yield and cost related. Bringing in through silicon vias is a wonderful idea that will surely be adopted for the high-performance, high-priced solutions. But it will require innovation to keep yields high and costs low for commodity ICs with strict price windows.
How about the new transistor types? FinFETs are doable, but it may take awhile before the process flows are ironed out and yields reach acceptable levels. Perhaps a planar, fully depleted SOI approach could be less expensive for some vendors, providing the IP libraries can be more fully developed by the SOI camp.
How about the heterogeneous transistors, in which a germanium channel is deposited in the PFET and an InGaAs channel in the NFET? This approach uses a silicon wafer as the starting substrate, and requires deft deposition skills for the non-silicon channel materials used to boost mobilities in the critical circuits. In a sense, that path is already being trod by GlobalFoundries and others, which use a germanium-rich channel to boost hole mobilities at the 32/28nm generation. This subject will be taken up at Semicon West during a Tuesday TechXPOT, “Enabling Sub-22nm with New Materials and Processes” featuring Sematech’s Raj Jammy, Intel’s Kaizad Mistry, and Carlos Mazure of Soitec, among others.
450mm Wafer Transition
Semicon West is one of the best places to find out about the 450mm wafer transition. The 450mm Supply Chain Forum will be held on Thursday morning, featuring Michael Liehr, general manager of the Global 450 Consortium at Albany, N.Y., Ron Rinfret, 450mm program director at Intel, and Kirk Hasserjian, a vice president at Applied Materials, among others.
Unfortunately for the industry, the EUV and 450mm wafer transition questions have become co-mingled. ASML has spent roughly $2 billion (€1.5 billion) in development of EUV, and it needs to recoup those investments with the 300mm EUV scanners it is bringing to market starting this year.
Which perhaps creates another If-When question, this time for 450mm: IF EUV arrives on 300mm tools, WHEN will 450mm wafers be widely adopted?
Even good-humored Ben Franklin, I’d wager, would have a tough time figuring that one.