Chipworks Zooms In on Tri-gate
By David Lammers
Ever since Intel uncloaked its tri-gate transistor a year ago, technology watchers have had to make do with the few images Intel released at that time.
Now, the long-awaited Chipworks images are on-line, following the company’s initial teardown report (Intel’s 22nm tri-gate transistors exposed) posted Monday (April 23). One initial surprise was the shape of the Intel fin, rounded on top and tapered or sloped on the sides.
Chipworks senior technology analyst (and chief blogger) Dick James said the 22nm teardown process got started when he saw a review of an Intel 22nm server chip on the Anandtech site, which included a helpful link to a site in Hong Kong which had the server processors for sale, even though the server MPUs are not officially on sale until June.
Chipworks (Ottawa) ordered half a dozen of the Intel Xeon E3-1230V2 Server CPUs, at $300 per processor, and they arrived on April 1. Though Chipworks has been burned before with counterfeit die inside packages with new markings, the 22nm chips from Tao Bao in Hong Kong turned out to be genuine, and Chipworks went back and bought more.
Fortunately, Chipworks had upgraded its transmission electron microscope (TEM) in January, replacing an out-of-date model with an FEI Osiris TEM, a much more automated system. The new TEM pumps down to a vacuum state more quickly, and alignment checking also is automated.
The Osiris TEM can do 400,000-times magnification. However, the microscope requires a sample thickness of about 80nm, which means that the images of the Intel transistors show more than is sometimes optimum: with a fin shown next to a gate, for example. “While the fin may be only 5-15nm wide, the sample has to be 80nm thick to get it in to the TEM. That increases the difficult of imaging. You are always seeing a gate and the fin, for example,” James said.
Looking at finFETs takes some getting used to, compared with planar transistors. “You definitely have got to be able to think in 3D. With a regular transistor I can explain how it works with one cross section. With finFETs, I need one image to show the shape of the fin, and another to show the shape of the gate, in right angles to each other. It is a bit more complicated from that point of view,” said James, who has worked for 17 years at Chipworks after earlier employment at semiconductor fabs in his native England.
Another complication is that the one-to-one ratio between structures and transistors doesn’t apply. One transistor can have multiple fins — six or more — while one fin can have multiple transistors.
Since each fin is a defined height and width, designers use quantized fins to create a wider PMOS, for example. “It is a whole different ballgame. These are quantized transistors, so the designers have to think in multiples of a single unit,” James said.
The Virtues of a Tapered Fin
The Chipworks images show an Intel transistor with a rounded top and tapered, sloping sides. James said that was an interesting and surprising early observation, because many of the photos of finFETs shown in recent years at IEDM and other conferences — by Sematech, Imec, TSMC, and others — all have shown a vertical fin. Intel’s own schematic diagrams show an idealized structure with straight sides.
James speculated that Intel’s tapered fin is easier to manufacture, and the rounded top evens out the electric field at the top of the fin. “Any pointed surface has a higher electric field than a flat surface, so the rounded structure may even out the electric field between the fin and the gate. Our speculation about why it is rounded relates to the fact that if the transistor had square corners on the fin, it would crank up the electric field and make the device less reliable.”
Also, etching straight walls is difficult, making it likely that the etching steps are probably easier with a tapered fin. James said flash memories also often have rounded corners in order to avoid damaging the gate dielectric on the memory cell.
The gate oxide and metal gate are much the same as Intel’s earlier planar transistor, and the PMOS stressing mechanisms also are similar. Intel appears to have changed the metal fill at the center of the gate, using tungsten instead of aluminum and titanium aluminum. James said they feel fairly confident of that conclusion because the “very dark” area appears to be the same color as the W contacts.
On the other hand, Chipworks at this point has “no idea what the stress mechanisms for NMOS are.” Intel is no longer using the nitride stressors it employed at the 90nm and 65nm nodes, because there is not enough room around the gate. At 45nm, Intel used a mixture of metals on the gate to put tensile stress on the channel. “That may be possible (with tri-gate), but it doesn’t show. If there is stress in the NMOS, it is different from the 32nm approach,” he said.
I asked James if Intel’s technologists cooperate with Chipworks as it struggles to figure out what the images show. He said he posts the blogs first, and hopes for some reaction steering him in the right direction later, if the initial conclusions are faulty.
“Sometimes one or another person from Intel will get back to me, and say, ‘I can’t tell you where you were wrong, but this is not quite right. And they are fairly cordial when I meet them at IEDM. When I am chatting with them, they might say ‘You are pretty well right 90 percent of the time,’ which I take as a compliment since we are groping in the dark on something like this.”