By David Lammers
Serge Biesemans, vice president of technology at Imec (Leuven, Belgium), was always among the first to arrive for the IEDM conference each December. Getting the proceedings before nearly everyone else, he retreated to his hotel room and spent most of the night reading the most-significant papers about transistor scaling. The thick IEDM book (distributed as a digital document on a thumb drive since 2009) was festooned with post-it notes by the time IEDM kicked off, clutched to Biesemans’ chest as he moved around for the rest of the conference.
With a new job at Imec now, Biesemans’ reading habits may change a bit.
Biesemans, and his colleague Rudi Cartuyvels, an interconnect expert, were in the thick of the research efforts leading to new transistor architectures. They lived and breathed scaling, and an interview with Biesemans was a fast-paced but friendly exchange on how transistors would move to the 20- or 14-nm nodes.
So I was surprised to catch up with Biesemans and Cartuyvels — in separate meetings at Imec’s headquarters a few weeks ago – and learn that they have very recently moved from the transistor scaling effort to Imec’s More Than Moore initiative headed up by Stephane Donnay. (Imec calls it CMORE).
It is well known that the European public and private R&D budgets have tilted towards More Than Moore, and to great success. Integrating sensors, MEMS, CMOS imaging devices, silicon photonics, and analog have bolstered Europe’s electronics industry, at a time when the European chip industry has largely shied away from chasing Moore’s Law scaling in memories and MPUs.
To be sure, Imec, with some 2,000 employees and a budget of 300 million Euros (about $420 million) continues to spend heavily on CMOS scaling. Imec CEO Luc van den Hove plans to expand the cleanroom space and build a 450mm line for the key process modules over the next few years, taking lithography, etch, cleaning, and other process steps to leading-edge design rules on the larger wafers.
Van den hove has recruited capable new managers, including An Steegen from IBM as the senior vice president of process technology and Aaron Thean from Freescale-IBM-Qualcomm as logic program director.
Nevertheless, the transfer of Biesemans and Cartuyvels to the More than Moore side of Imec is a telling event. CMOS scaling is becoming harder to achieve, and the ITRS scaling roadmap is being driven by the capabilities of the process equipment, including EUV lithography. Process development increasingly involves the discovery and integration of new materials.
As Imec stays on the scaling path, new opportunities are developing in heterogeneous integration, the More Than Moore side of the house. Interestingly, Imec is taking a different business approach there, one based on bilateral product development. CMOS scaling largely involves the major IC vendors working cooperatively on Imec’s “Core CMOS” program. (Only IBM, Toshiba/Sandisk, and UMC are thus far absent from Imec’s Core CMOS program, with Intel, GlobalFoundries, TSMC, and Samsung among the participants.)
Imec also has a multi-company GaN effort underway, aimed at developing processes based on 200mm gallium nitride substrates. The GaN project seeks to move the manufacturing of light emitting diodes from old 4-inch production lines to more-modern 200mm platforms, preparing for the era perhaps a decade hence when LED-based lighting will dominate.
For most of the More Than Moore projects, Imec works with a single partner, and the goal is to develop a commercial product. The first such product was a multi-chip set of sensors co-developed with ASML to monitor the EUV dose and alignment. Four blocks of three sensors measure the overlay and CD control of the EUV scanners, providing feedback to the tool.
“This is a fairly critical component for the EUV scanners ASML is shipping now, and there is good revenue from it for Imec. We are looking at development projects like that, doing things that no one else can do,” he said.
Other product-oriented projects involve optical interconnect ICs, and several biosensors. “We want to leverage our silicon platform, leveraging CMOS capabilities for non-CMOS ICs. We have several projects underway with partners for biosensors, and we are learning, for example, how to measure light as it moves in and out of blood. My job is to develop the processes, using our 200mm fab, so these biosensor products can be put into very high-volume manufacturing at low costs,” Biesemans said.
Opto-electronics is another big opportunity, particularly for the high-end industrial and medical equipment industries where are a European strength. These are, he said, “low volume but high ROI” projects. MEMS are another high-volume opportunity which plays into Imec’s silicon processing strengths.
Biesemans said he spent the last 22 years working on CMOS scaling, 14 of those years at IBM, Sony, and Panasonic, and eight thus far at Imec. He welcomes a change.
“We don’t know where CMOS scaling will stop,” he said, shaking off questions about whether the end of CMOS is near or far and suggesting that too many people confuse Moore’s Law with lithographic scaling.
“We do know that 3D is one way to delay the end of Moore’s Law, including TSVs. Moore’s Law will continue in some form, even as miniaturization slows down. That is where 3D and More Than Moore comes in.”