Welcome to SemiMD
Welcome to SemiMD (Semiconductor Manufacturing and Design), a new Web site/portal/community.
Our mission is to cover news and examine trends facing the semiconductor manufacturing community, including equipment, materials, process technology, fabs, market trends, DFM and manufacturing-related software. I hope you all will feel welcome to provide us with scintillating suggestions or lively story ideas.
At IEDM in San Francisco in early December, I got a better view of the daunting technical challenges facing the semiconductor industry: the supply side. I came back to Austin and got a view of the demand side: the holiday wish lists from my family, asking for smart phones, tablets, bigger hard drives on faster desktops, and the like.
The demand matches up well with the very expensive engineering projects facing the suppliers, ranging from 450 mm equipment to EUV lithography. As IBM’s senior manager of device technology research manager Mukesh Khare put it, “the industry is now big enough, with enough engineering talent, to extend scaling.”
Here are just a few of the topics we will be following at SemiMD this year.
High-k. This is a cost-conscious industry, especially when it comes to high-volume consumer ICs. At IEDM, Qualcomm presented its 28nm low-power process, based on a SiON gate stack. Qualcomm’s P.R. Chidambaram explained how a 28nm high-k foundry process needs to be well wrung out for the huge volumes Qualcomm enjoys. Volume high-k introduction is one of the topics we will be watching at SemiMD in 2011.
EUV. Lithography challenges also are high on our story list. At IEDM, Intel fellow and director of lithography Sam Sivakumar described EUV as being “on the brink of being available” but said its introduction “depends on the cost of ownership.” The chip industry faces “a year or two of data collection” on EUV scanners, Sivakumar added.
FinFETs v. ETSOI. This is another richly interesting debate. Do transistors go vertical, with the high performance possible when the gate wraps around a fin-like channel? Or will it prove too difficult to control fin heights and widths, squeeze in the contacts, and overcome FinFET manufacturing challenges? At IEDM, STMicro’s director of advanced devices, Thomas Skotnicki, presented the case for extremely thin silicon-on-insulator, arguing that biasing a bottom gate will give ETSOI a performance advantage.
TSVs. Through-silicon-vias are another game-changer we will be watching. No doubt they will happen, but getting costs down is the story to watch here.
I find it interesting that people in the chip industry divide into the optimists (“we will find a way to do it, we always have”) and the not-so-optimistic folks, who often point to the “laws of physics” or “economics.”
This year, 2011, is a time when the optimists will be tested. And that is where SemiMD comes in: telling the stories of how people and companies bring new technical knowledge to bear on market opportunities. Keep in touch. We welcome your participation.
- David Lammers