GlobalFoundries has fully transformed itself into a pure-play foundry, now that the company’s Fab1 in Dresden is well past being an AMD line running a single product. As disclosed at the company’s Global Technology Conference held Aug. 30th in Santa Clara, California, Fab1 now runs 45, 32, and 28nm node processes for multiple customers. “Out customer base is primarily in the U.S., like the leading foundry in Taiwan,” explained ATIC board member and temporary CEO Ajit Manocha.

In marvelous Malta, N.Y., the company continues to build Fab 8. It will be a “lights out” fab without even the need for “operator assisted” running of the tools in the line. The base build was completed two months ahead of schedule, in preparation for cleanroom area equal to six American football fields. First silicon is planned for November 2011, with 60,000 wafers-per-month starting to ramp at 32nm in the summer of 2012.

Leading edge today means 32/28nm node processing, and GlobalFoundries offers multiple process flow variations to meet distinctly different end-market needs. The company’s 32nm HKMG processes on 300mm SOI wafers do not use strain engineering. However, after joint-development with Samsung in Korea, there will be embedded silicon-germanium (e-SiGe) stressors for 28nm chips. The 28nm processes will run at Fab 1 and Fab 8, and also at Samsung’s S1 in Kiheung and S2 in Austin.

Mainstream today generally means 65nm node processing, as discussed during an end-of-day panel discussion moderated by SemiMD’s Ed Sperling. Half of the global volume of ARM chips that shipped last year were ARM7, many running in Singapore Fab 7. “Customers are doing a lot of very cool things that are relevant today at 65nm,” commented GlobalFoundries’ Walter Ng. “That is what pays the bills.” One cool thing is a low-power CMOS photonics 40 Gb/s optical interconnect made by LightWire using one 130nm plus one 65nm SoC chip.

The company is engaged in R&D from universities to apps labs, and has different teams collaborating on process, design, and manufacturing improvements. The R&D ecosystem for GlobalFoundries has expanded beyond the IBM Common Platform Alliance and now includes IMEC, Intermolecular, and PDF Solutions.

–Ed Korczynski

“The difficult we do immediately, the impossible takes longer” is a quote ascribed to different individuals in history. The sentiment is surely felt in the hearts of the valiant engineers working overtime to create vital new manufacturing technologies for IC production. Of all the new engineering challenges, few push the boundaries of the possible like creating extreme ultra-violet (EUV) sources for high-volume manufacturing (HVM).

EUV lithography requires the entire infrastructure of exposure tools, masks, sources, and resist. Ron Kool directs product marketing for EUV tool developer ASML, and we had a brief chance to chat during SEMICON West about the engineering challenges of EUV source hardware. There are two ways that tin (Sn) is used to create a beam of electro-magnetic energy for EUV steppers: laser pulsed plasma (LPP) and electrical-Discharge Produced Plasma (DPP). In both, a liquid Sn plasma is pulsed with energy so that electron decay emits a pulse of ~13.5nm wavelength EUV. The source sub-systems must balance material flows, laser beams, energy pulses, and cooling at incredibly high speeds.

Kool acknowledged that these source technologies look dauntingly complex, but no more so than the water immersion 193nm (193i) steppers that are the current industry work-horses. If we remember back to the first pilot line work on 193i, the engineering challenges appeared nearly impossible: reduced throughput, uncontrolled yield losses, and serious resist issues. All those problems were solved.

During the week of SEMICON West this year, Gigaphoton announced that its original technology for mitigating debris with magnetic fields for laser-produced plasma (LPP) sources is successfully removing 92% of Sn debris. Scheduled to be shipped in the beginning of 2012, this announcement verifies that Gigaphoton has proven its technology a number of times. Details of Gigaphoton’s plans to reach 250W output power, along with the most recent results for the Cymer and Xtreme EUV sources, were reported on earlier this year by M. David Levenson at BetaSights. No worries, the industry is once again engineering the impossible.

–Ed Korczynski

Intel’s trumpeting of 22nm CMOS finFETs as the future-arrived-in-the-present has triggered TSMC and GlobalFoundries to say that the present is planar. The present will remain planar for commercial IC foundries for another node or so to preserve flexibility in design. Since Intel has one major IC product family, it could more easily re-tune it’s designs and manufacturing to work with finFETs.

On May 5 of this year, Dow Jones Newswires in Taiwan published an official comment on finFETs at the 22/20nm node by TSMC senior vice president of research and development S.Y. Chiang. Despite showing excellent 20nm CMOS finFET transistor performance at IEDM 2010, in terms of design, “the tools and layout for the technology are still immature at the moment,” said Chiang. “The current 2D transistor will hit its limit when the production process advances beyond 20nm and that’s when we will switch to 3D transistors.”

GlobalFoundries recently published a newsletter in which it declared that planar CMOS provides the best balance of cost, risk, and performance for 22/20nm node ICs. The company says that customers’ design requirements across diverse product types—including computing, consumer, and communications chips—led to the decision to push out finFETs until the 16/14nm node. All leading-edge IC foundries today must offer more than just fab capacity, however, so GlobalFoundries is already working on a full suite of design tools for 22/20nm.

As a partner in the Joint Development Alliance (JDA) centered around IBM, GlobalFoundries has access to over a decade of research in finFET technology and can choose to use it when it may be needed. The JDA’s collaborative decision to continue with 2D planer structures in 20nm was based on the power, performance, and cost parameters that drive the specifications for the global industry, from high performance desktop computing to low power mobile applications.

-Ed Korczynski

By now, you’ve probably heard that Intel has uncloaked “tri-gate” finFET (a.k.a. Multi-Gate FET or MuGFET) architectures as the company’s 22nm transistor technology for high-volume manufacturing (HVM) of digital ICs. This confirms the rumors that have spread for the last half-year, and proves that this pseudo-3D approach will finally live outside of R&D labs. With much of the IC fab world focusing on low-power chips for mobile applications, the fully-depleted channels of finFETs provide reduced power consumption.

To be sure finFETs are a very attractive way to get to fully-depleted channels and so achieve the lowest possible off-current in transistors. At last year’s IEDM, with rumors of this move by Intel rampant, there was much hallway conversation about the relative merits and demerits of wrapping gates around a fin. In general, there are 2nd-order electrostatic issues associated with the 3D structures so that new possible leakage paths must be controlled. An IEDM evening panel discussion sponsored by Applied Materials featured a discussion on finFETs vs. FD-SOI vs. alternate-channel materials for 22nm node processing. Witek Maszara of GlobalFoundries explained that, “Better electrostatics could come from FD or MuGFET devices, while better transport could come from high-mobility channels.”

Intel first showed tri-gate finFETs for SRAMs in 2006, and claims that only 2-3% additional processing costs are needed to go from planar FETs in high-volume. Consequently, the major advantage of finFETs at 22nm is that no new channel materials will have to be integrated, and the extra cost of silicon-on-insulator wafers can be skipped. Intel did not mention the costs associated with re-spinning all of their designs to be able to go from planar to fins (this will be the topic of a future Siliconisms blog post). To be sure, old planar transistor models must be replaced.

Intel’s promotion of this transistor architecture includes extensive mention of Atom chips and mobile applications. The company clearly wants everyone to still think of Intel when we think of mobile computing, despite the stunning failures of Atom chips to compete with ARM-cores in the last few years. The raw transistor performance boost of 22nm finFETs will certainly provide an advantage over 32nm planar FETs, and so Intel’s less-efficient Atom chips may win some sockets from the ARM hordes while the rest of the industry catches up to 22nm.

-Ed Korczynski