GlobalFoundries has fully transformed itself into a pure-play foundry, now that the company’s Fab1 in Dresden is well past being an AMD line running a single product. As disclosed at the company’s Global Technology Conference held Aug. 30th in Santa Clara, California, Fab1 now runs 45, 32, and 28nm node processes for multiple customers. “Out customer base is primarily in the U.S., like the leading foundry in Taiwan,” explained ATIC board member and temporary CEO Ajit Manocha.

In marvelous Malta, N.Y., the company continues to build Fab 8. It will be a “lights out” fab without even the need for “operator assisted” running of the tools in the line. The base build was completed two months ahead of schedule, in preparation for cleanroom area equal to six American football fields. First silicon is planned for November 2011, with 60,000 wafers-per-month starting to ramp at 32nm in the summer of 2012.

Leading edge today means 32/28nm node processing, and GlobalFoundries offers multiple process flow variations to meet distinctly different end-market needs. The company’s 32nm HKMG processes on 300mm SOI wafers do not use strain engineering. However, after joint-development with Samsung in Korea, there will be embedded silicon-germanium (e-SiGe) stressors for 28nm chips. The 28nm processes will run at Fab 1 and Fab 8, and also at Samsung’s S1 in Kiheung and S2 in Austin.

Mainstream today generally means 65nm node processing, as discussed during an end-of-day panel discussion moderated by SemiMD’s Ed Sperling. Half of the global volume of ARM chips that shipped last year were ARM7, many running in Singapore Fab 7. “Customers are doing a lot of very cool things that are relevant today at 65nm,” commented GlobalFoundries’ Walter Ng. “That is what pays the bills.” One cool thing is a low-power CMOS photonics 40 Gb/s optical interconnect made by LightWire using one 130nm plus one 65nm SoC chip.

The company is engaged in R&D from universities to apps labs, and has different teams collaborating on process, design, and manufacturing improvements. The R&D ecosystem for GlobalFoundries has expanded beyond the IBM Common Platform Alliance and now includes IMEC, Intermolecular, and PDF Solutions.

–Ed Korczynski

UPDATED 5/6/2011

Intel’s 22nm node “tri-gate” finFETs have gotten a lot of coverage in the both the technology and mainstream press. As usual, the mainstream press is lucky to be able to pass along IC fabrication details without distortion. The New York Times’ John Markoff provides the best mainstream coverage, in part because he quotes SemiMD’s Editor-in-Chief David Lammers and provides a link to the deep commentary and analysis you can only find here on this site.

For example, SemiMD has already reported on Applied Materials’ deal to buy Varian Semiconductor Equipment, which is influenced by Varian’s strong intellectual property (IP) position in the one critical piece of manufacturing technology needed to make finFETs in high-volumes: plasma doping. Note that Applied Materials recently released it’s own Conformal Plasma Doping chamber for the Centura cluster platform, and will presumably integrate Varian technology into it’s own.

For over five years, Varian has been selling PLAD tools to DRAM fabs where extremely high doses of boron are needed for a Dual Poly Gate implant step. This has proven the capability of the tool, but most other implant steps in ICs today have continued to use scanning beam-line implant tools as processes of record (POR) for HVM. However, when transistor channels protrude above the wafer surface like fins the old beam-lines cannot uniformly implant all sides of the fin at once. Plasma doping tools, unlike beam-lines, implant the whole wafer and all exposed surfaces at once and so can easily handle implants into and adjacent-to fins. However, beam-line implanters can dope finFITs, too.

Intel claims that 22nm node finFETs will cost only 2-3% more in HVM compared to 22nm node planar FETs in bulk silicon. The only One way Intel can keep the finFET fab costs down is by using plasma-doping implant chambers. Based on presentations at previous IEDM conferences, finFETs seem to be able to use the most of the same materials and processes as for planar transistors, including high-k metal-gates. However, the change in geometry means that changes will be needed to integrate materials for strained-silicon. Processing details should start leaking over the next year.

-Ed Korczynski

By now, you’ve probably heard that Intel has uncloaked “tri-gate” finFET (a.k.a. Multi-Gate FET or MuGFET) architectures as the company’s 22nm transistor technology for high-volume manufacturing (HVM) of digital ICs. This confirms the rumors that have spread for the last half-year, and proves that this pseudo-3D approach will finally live outside of R&D labs. With much of the IC fab world focusing on low-power chips for mobile applications, the fully-depleted channels of finFETs provide reduced power consumption.

To be sure finFETs are a very attractive way to get to fully-depleted channels and so achieve the lowest possible off-current in transistors. At last year’s IEDM, with rumors of this move by Intel rampant, there was much hallway conversation about the relative merits and demerits of wrapping gates around a fin. In general, there are 2nd-order electrostatic issues associated with the 3D structures so that new possible leakage paths must be controlled. An IEDM evening panel discussion sponsored by Applied Materials featured a discussion on finFETs vs. FD-SOI vs. alternate-channel materials for 22nm node processing. Witek Maszara of GlobalFoundries explained that, “Better electrostatics could come from FD or MuGFET devices, while better transport could come from high-mobility channels.”

Intel first showed tri-gate finFETs for SRAMs in 2006, and claims that only 2-3% additional processing costs are needed to go from planar FETs in high-volume. Consequently, the major advantage of finFETs at 22nm is that no new channel materials will have to be integrated, and the extra cost of silicon-on-insulator wafers can be skipped. Intel did not mention the costs associated with re-spinning all of their designs to be able to go from planar to fins (this will be the topic of a future Siliconisms blog post). To be sure, old planar transistor models must be replaced.

Intel’s promotion of this transistor architecture includes extensive mention of Atom chips and mobile applications. The company clearly wants everyone to still think of Intel when we think of mobile computing, despite the stunning failures of Atom chips to compete with ARM-cores in the last few years. The raw transistor performance boost of 22nm finFETs will certainly provide an advantage over 32nm planar FETs, and so Intel’s less-efficient Atom chips may win some sockets from the ARM hordes while the rest of the industry catches up to 22nm.

-Ed Korczynski