Intel 22nm finFET processing
UPDATED 5/6/2011
Intel’s 22nm node “tri-gate” finFETs have gotten a lot of coverage in the both the technology and mainstream press. As usual, the mainstream press is lucky to be able to pass along IC fabrication details without distortion. The New York Times’ John Markoff provides the best mainstream coverage, in part because he quotes SemiMD’s Editor-in-Chief David Lammers and provides a link to the deep commentary and analysis you can only find here on this site.
For example, SemiMD has already reported on Applied Materials’ deal to buy Varian Semiconductor Equipment, which is influenced by Varian’s strong intellectual property (IP) position in the one critical piece of manufacturing technology needed to make finFETs in high-volumes: plasma doping. Note that Applied Materials recently released it’s own Conformal Plasma Doping chamber for the Centura cluster platform, and will presumably integrate Varian technology into it’s own.
For over five years, Varian has been selling PLAD tools to DRAM fabs where extremely high doses of boron are needed for a Dual Poly Gate implant step. This has proven the capability of the tool, but most other implant steps in ICs today have continued to use scanning beam-line implant tools as processes of record (POR) for HVM. However, when transistor channels protrude above the wafer surface like fins the old beam-lines cannot uniformly implant all sides of the fin at once. Plasma doping tools, unlike beam-lines, implant the whole wafer and all exposed surfaces at once and so can easily handle implants into and adjacent-to fins. However, beam-line implanters can dope finFITs, too.
Intel claims that 22nm node finFETs will cost only 2-3% more in HVM compared to 22nm node planar FETs in bulk silicon. The only One way Intel can keep the finFET fab costs down is by using plasma-doping implant chambers. Based on presentations at previous IEDM conferences, finFETs seem to be able to use the most of the same materials and processes as for planar transistors, including high-k metal-gates. However, the change in geometry means that changes will be needed to integrate materials for strained-silicon. Processing details should start leaking over the next year.
-Ed Korczynski
Tags: 22nm, Applied Materials, beam-line, CMOS, Conforma, CPD, finFET, HVM, IC, implant, Intel, PLAD, POR, TSMC, Varian, VSEA