EbDW may sneak in behind masks
Electron-beam Direct Write (EbDW) lithography on commercial wafers may sneak in the industry behind the technology developments for mask writing. At SPIE AL this year, Aki Fujimora (CEO of D2S and head of the E-beam Initiative) talked with SemiMD about solving today’s mask problems using tricks that will be needed before EbDW can be used in HVM. D2S’ Model-Based Mask-Data Preparation (MB-MDP) software was reported by one IBM engineer to cut up to ½ of the time from mask writing. Xilinx is one of the newest partners in the E-beam Initiative, and as a company built to make some of the largest logic chips in the highest volumes, probably didn’t join because of EbDW.
CEA-Leti and its ASELTA Nanographics spin-out recently announced the start of joint work on e-beam proximity effects corrections for both mask writing and EbDW. A new lab will be staffed inside the multi-partner IMAGINE program, which is designed to develop maskless lithography for IC manufacturing using the Mapper tool. Mentor Graphics just joined IMAGINE, and will develop multiple e-beam lithography data processing flows in the program. “Multi-beam systems for maskless lithography are contenders for next-generation patterning. The IMAGINE program is offering a unique infrastructure to enable this technology and we want to be an early partner in this research,” said Joe Sawicki, vice president and general manager of Mentor’s Design to Silicon Division.
In his SPIE AL keynote, TSMC senior vice president of Research and Development Shang-yi Chiang explained the economic constraints when working on new lithography technologies. For a commercial foundry, the price a customer is willing to pay for a next generation wafer is limited by the price of the current generation. In TSMC’s internal budget for this overage, a full half is due to lithography. “Within transistor and interconnect we do not see any roadblocks,” said Chiang. “So lithography cost is the single greatest factor which may limit our ability to extend Moore’s Law into the next decade.” EbDW could be the only litho used for designs needing only hundreds of wafers, and could cut grid lines in HVM. A Mapper “pre-alpha” tool shipped into TSMC’s Fab12 in July 2009, and was exposing wafers by the end of the year using a 25nm spot size and raster scan writing into 45nm thick resist on BARC.
David Lam (yes, founder of Lam), currently executive evangelist for Silicon Valley start-up Multibeam, provided an excellent overview of the fundamental requirements and constraints of EbDW at SPIE this year. Referring to the term ‘complementary lithography,’ used last year by Yan Borodowsky (Intel’s expert, present in the audience) to describe 193i to form grids complemented by some other lithographic technology to perform sparse cuts, this year Lam tried out the term ‘Complementary E-Beam Lithography’ (CEBL) to mean EBL used in complement to 193i for low-density critical layers. “In my opinion this is the only way that e-beam litho can get into high-volume,” cautioned Lam.
-Ed Korczynski
Tags: 14nm, 20nm, 22nm, CEBL, Chiang, D2S, David Lam, HVM, IC, IMAGINE, Intel, Lam, Leti, litho, MAPPER, Mentor Graphics, Multibeam, NGL, TSMC
March 14th, 2011 at 2:22 am
The bigger challenge facing multibeam pattern generators for masks is development and scaleup cost vs. demand. The pattern generator business has never returned the cost of capital to its investors, and only early investors in Etec (and at least one key manager)made money on its IPO. It is a market that is both extremely demanding and low volume.