Common Partners 2Xnm to be gate-last
Ever since Intel pulled Gordon Moore out of retirement to declare that high-k metal-gate (HKMG) transistors were the biggest change to hit the IC industry since the the MOSFET, there has been a battle between Intel and IBM as to which way to go. Intel started at the 4Xnm node with gate-last processing, in which the transistor gate is made after high-temperature anneals, and will continue to use gate-last at 3Xnm and 2Xnm nodes. IBM et al. kept SiON gates at 4Xnm, decided to go with gate-first HKMG at 3Xnm, but has now admitted to rumors that 2Xnm will require a reversal of direction to gate-last.
At the Common Platform (CP) Technology Day in Santa Clara, California last month, representatives of foundry-partners BM, Samsung, and GlobalFoundries discussed the rational for switching between gate-first at 3Xnm and gate-last at 2Xnm. In general, gate-last flows add in two new CMP process steps, while gate-first flows add complexity to the existing process steps. However, gate-last requires relatively greater restrictions on the design rules and re-design of circuitry, such that the areas of chips may increase by 10-20% compared to gate-first. Thus gate-first at 3Xnm can promise a greater number of chips/wafer.
Gate-first at 3Xnm allows for design cost savings when shrinking 4Xnm SiON chips, since poly-jogs and other 2D shapes may still be used. In contrast, 3Xnm gate-last mandates use of extremely restrictive design rules (RDR) such that only 1D line segments may be used in any one layer. RDRs impose additional design costs and final chip area penalties, though generally providing improved fab yield. Since most Intel chips are designed internally, the company can tightly integrate design and manufacturing teams and so can more easily work with RDR compared to others.
Why now plan to use gate-last at 2Xnm? The lithographic process window is stuck with immersion-193nm illumination, such that 2D shapes cannot be formed at 2Xnm. “In density, for 32/28nm gate-first was the best. Different things happen at 20nm, and we had to do local interconnects, so the RDRs limited density,” explained Gary Patton, IBM vice president of semiconductor R&D.
Meanwhile, TSMC will continue to use gate-last at both nodes, potentially saving design costs for shrinks between nodes. Rival foundry UMC, with a hybrid “first+last” flow announced for 3Xnm, will presumably follow with gate-last for 2Xnm. –Ed Korczynski