The lithographers return each February (28^th through March 3^rd this year) to San José (California) for the SPIE conference, in part to see the exhibition of the best new tools and the brightest new sources for patterning nano-scale devices. With multiple technical sessions in parallel, poster/snack sessions, workshops, and evening roundtables it’s a feast for anyone working near fabs, not just lithographers: depositions and etches are key to double-patterning (DP), metrology limits are explored, and designs’ EDA PDK DFM extensions gate yield. From the advance program available online, we can extract some obvious trends, and also spotlight some sessions and presentations as “must sees.”

With the source wavelength stuck in water at 193nm, and all post-optical “next-generation lithography” (NGL) technologies still stuck in R&D, the only way today to form 32nm and smaller structures is to use clever extensions to optical litho like DP and source-mask-optimization (SMO). Such extensions require integration of design and manufacturing technologies to an ever greater extent. DFM is only possible with accurate fab data, so as we push to make ever smaller devices we find the need for ever more capable measuring tools.

EUV has missed the boat for 22/20nm node production, since that process is now in pilot. Thus, the next possible insertion point is the 16/14nm node, which alert readers will notice is almost the same size as the 13.5 nm wavelength of EUV. Since an expensive technology must be useful for more than a few years, whatever patterning technology is developed for 16nm must be extendible to 11nm at least. Consequently, EUV litho will need to be able to be able to pattern below wavelength, which will require greater expense in design (OPC and SRAF), and in manufacturing (more complex and thus more expensive tooling needed). Wikipedia sums up the EUV challenges well.

Big picture trend info will be provided in plenary presentations by Luc Van den hove (President and CEO, IMEC) and Shang-Yi Chiang (Senior Vice President, R&D, TSMC) that start the conference off Monday morning. At the risk of offending by omission, the following are some of the best invited papers at SPIE AL this year:

• Alain Diebold (U.Albany) on “Semiconductor metrology from new transistor and interconnect materials to future nanostructures” [7971-01] MON AM,
• Patrick Naulleau (LBNL) on “Critical challenges for EUV resist materials” [7972-02] MON AM,
• Roel Gronheid (IMEC) on “EUV secondary electron blur at the 22-nm half-pitch node” [7969-03] MON PM,
• Kiyoshi Takamasu (U.Tokyo) on “Subnanometer line width and line profile measurement for CD-SEM calibration by using STEM” [7971-07] MON PM,
• Aki Fujimura (D2S) on “A comparison of maskless technologies” [7970-02] TUE AM,
• Cyrus Tabery (GlobalFoundries) on “Design architecture, metrology, and integration: OPC at the age of discovery” [7973-02] TUE AM,
• Robert Socha (ASML) on “Freeform and SMO” [7973-04] TUE AM,
• Chris Bencher (Applied Materials) on “Mandrel-based patterning: density multiplication techniques for 15-nm nodes” [7973-19] WED AM,
• Mark Bohr (Intel) on “Moore’s Law in the innovation era” [7974-01] WED PM,
• Lars Leibmann (IBM) on “Decomposition-aware DRC to enable double-patterning compliant standard cell libraries” [7974-19] THU PM.

–Ed Korczynski

Ever since Intel pulled Gordon Moore out of retirement to declare that high-k metal-gate (HKMG) transistors were the biggest change to hit the IC industry since the the MOSFET, there has been a battle between Intel and IBM as to which way to go. Intel started at the 4Xnm node with gate-last processing, in which the transistor gate is made after high-temperature anneals, and will continue to use gate-last at 3Xnm and 2Xnm nodes. IBM et al. kept SiON gates at 4Xnm, decided to go with gate-first HKMG at 3Xnm, but has now admitted to rumors that 2Xnm will require a reversal of direction to gate-last.

At the Common Platform (CP) Technology Day in Santa Clara, California last month, representatives of foundry-partners BM, Samsung, and GlobalFoundries discussed the rational for switching between gate-first at 3Xnm and gate-last at 2Xnm. In general, gate-last flows add in two new CMP process steps, while gate-first flows add complexity to the existing process steps. However, gate-last requires relatively greater restrictions on the design rules and re-design of circuitry, such that the areas of chips may increase by 10-20% compared to gate-first. Thus gate-first at 3Xnm can promise a greater number of chips/wafer.

Gate-first at 3Xnm allows for design cost savings when shrinking 4Xnm SiON chips, since poly-jogs and other 2D shapes may still be used. In contrast, 3Xnm gate-last mandates use of extremely restrictive design rules (RDR) such that only 1D line segments may be used in any one layer. RDRs impose additional design costs and final chip area penalties, though generally providing improved fab yield. Since most Intel chips are designed internally, the company can tightly integrate design and manufacturing teams and so can more easily work with RDR compared to others.

Why now plan to use gate-last at 2Xnm? The lithographic process window is stuck with immersion-193nm illumination, such that 2D shapes cannot be formed at 2Xnm. “In density, for 32/28nm gate-first was the best. Different things happen at 20nm, and we had to do local interconnects, so the RDRs limited density,” explained Gary Patton, IBM vice president of semiconductor R&D.

Meanwhile, TSMC will continue to use gate-last at both nodes, potentially saving design costs for shrinks between nodes. Rival foundry UMC, with a hybrid “first+last” flow announced for 3Xnm, will presumably follow with gate-last for 2Xnm. –Ed Korczynski