GlobalFoundries has fully transformed itself into a pure-play foundry, now that the company’s Fab1 in Dresden is well past being an AMD line running a single product. As disclosed at the company’s Global Technology Conference held Aug. 30th in Santa Clara, California, Fab1 now runs 45, 32, and 28nm node processes for multiple customers. “Out customer base is primarily in the U.S., like the leading foundry in Taiwan,” explained ATIC board member and temporary CEO Ajit Manocha.

In marvelous Malta, N.Y., the company continues to build Fab 8. It will be a “lights out” fab without even the need for “operator assisted” running of the tools in the line. The base build was completed two months ahead of schedule, in preparation for cleanroom area equal to six American football fields. First silicon is planned for November 2011, with 60,000 wafers-per-month starting to ramp at 32nm in the summer of 2012.

Leading edge today means 32/28nm node processing, and GlobalFoundries offers multiple process flow variations to meet distinctly different end-market needs. The company’s 32nm HKMG processes on 300mm SOI wafers do not use strain engineering. However, after joint-development with Samsung in Korea, there will be embedded silicon-germanium (e-SiGe) stressors for 28nm chips. The 28nm processes will run at Fab 1 and Fab 8, and also at Samsung’s S1 in Kiheung and S2 in Austin.

Mainstream today generally means 65nm node processing, as discussed during an end-of-day panel discussion moderated by SemiMD’s Ed Sperling. Half of the global volume of ARM chips that shipped last year were ARM7, many running in Singapore Fab 7. “Customers are doing a lot of very cool things that are relevant today at 65nm,” commented GlobalFoundries’ Walter Ng. “That is what pays the bills.” One cool thing is a low-power CMOS photonics 40 Gb/s optical interconnect made by LightWire using one 130nm plus one 65nm SoC chip.

The company is engaged in R&D from universities to apps labs, and has different teams collaborating on process, design, and manufacturing improvements. The R&D ecosystem for GlobalFoundries has expanded beyond the IBM Common Platform Alliance and now includes IMEC, Intermolecular, and PDF Solutions.

–Ed Korczynski

“The difficult we do immediately, the impossible takes longer” is a quote ascribed to different individuals in history. The sentiment is surely felt in the hearts of the valiant engineers working overtime to create vital new manufacturing technologies for IC production. Of all the new engineering challenges, few push the boundaries of the possible like creating extreme ultra-violet (EUV) sources for high-volume manufacturing (HVM).

EUV lithography requires the entire infrastructure of exposure tools, masks, sources, and resist. Ron Kool directs product marketing for EUV tool developer ASML, and we had a brief chance to chat during SEMICON West about the engineering challenges of EUV source hardware. There are two ways that tin (Sn) is used to create a beam of electro-magnetic energy for EUV steppers: laser pulsed plasma (LPP) and electrical-Discharge Produced Plasma (DPP). In both, a liquid Sn plasma is pulsed with energy so that electron decay emits a pulse of ~13.5nm wavelength EUV. The source sub-systems must balance material flows, laser beams, energy pulses, and cooling at incredibly high speeds.

Kool acknowledged that these source technologies look dauntingly complex, but no more so than the water immersion 193nm (193i) steppers that are the current industry work-horses. If we remember back to the first pilot line work on 193i, the engineering challenges appeared nearly impossible: reduced throughput, uncontrolled yield losses, and serious resist issues. All those problems were solved.

During the week of SEMICON West this year, Gigaphoton announced that its original technology for mitigating debris with magnetic fields for laser-produced plasma (LPP) sources is successfully removing 92% of Sn debris. Scheduled to be shipped in the beginning of 2012, this announcement verifies that Gigaphoton has proven its technology a number of times. Details of Gigaphoton’s plans to reach 250W output power, along with the most recent results for the Cymer and Xtreme EUV sources, were reported on earlier this year by M. David Levenson at BetaSights. No worries, the industry is once again engineering the impossible.

–Ed Korczynski

Intel’s trumpeting of 22nm CMOS finFETs as the future-arrived-in-the-present has triggered TSMC and GlobalFoundries to say that the present is planar. The present will remain planar for commercial IC foundries for another node or so to preserve flexibility in design. Since Intel has one major IC product family, it could more easily re-tune it’s designs and manufacturing to work with finFETs.

On May 5 of this year, Dow Jones Newswires in Taiwan published an official comment on finFETs at the 22/20nm node by TSMC senior vice president of research and development S.Y. Chiang. Despite showing excellent 20nm CMOS finFET transistor performance at IEDM 2010, in terms of design, “the tools and layout for the technology are still immature at the moment,” said Chiang. “The current 2D transistor will hit its limit when the production process advances beyond 20nm and that’s when we will switch to 3D transistors.”

GlobalFoundries recently published a newsletter in which it declared that planar CMOS provides the best balance of cost, risk, and performance for 22/20nm node ICs. The company says that customers’ design requirements across diverse product types—including computing, consumer, and communications chips—led to the decision to push out finFETs until the 16/14nm node. All leading-edge IC foundries today must offer more than just fab capacity, however, so GlobalFoundries is already working on a full suite of design tools for 22/20nm.

As a partner in the Joint Development Alliance (JDA) centered around IBM, GlobalFoundries has access to over a decade of research in finFET technology and can choose to use it when it may be needed. The JDA’s collaborative decision to continue with 2D planer structures in 20nm was based on the power, performance, and cost parameters that drive the specifications for the global industry, from high performance desktop computing to low power mobile applications.

-Ed Korczynski

UPDATED 5/6/2011

Intel’s 22nm node “tri-gate” finFETs have gotten a lot of coverage in the both the technology and mainstream press. As usual, the mainstream press is lucky to be able to pass along IC fabrication details without distortion. The New York Times’ John Markoff provides the best mainstream coverage, in part because he quotes SemiMD’s Editor-in-Chief David Lammers and provides a link to the deep commentary and analysis you can only find here on this site.

For example, SemiMD has already reported on Applied Materials’ deal to buy Varian Semiconductor Equipment, which is influenced by Varian’s strong intellectual property (IP) position in the one critical piece of manufacturing technology needed to make finFETs in high-volumes: plasma doping. Note that Applied Materials recently released it’s own Conformal Plasma Doping chamber for the Centura cluster platform, and will presumably integrate Varian technology into it’s own.

For over five years, Varian has been selling PLAD tools to DRAM fabs where extremely high doses of boron are needed for a Dual Poly Gate implant step. This has proven the capability of the tool, but most other implant steps in ICs today have continued to use scanning beam-line implant tools as processes of record (POR) for HVM. However, when transistor channels protrude above the wafer surface like fins the old beam-lines cannot uniformly implant all sides of the fin at once. Plasma doping tools, unlike beam-lines, implant the whole wafer and all exposed surfaces at once and so can easily handle implants into and adjacent-to fins. However, beam-line implanters can dope finFITs, too.

Intel claims that 22nm node finFETs will cost only 2-3% more in HVM compared to 22nm node planar FETs in bulk silicon. The only One way Intel can keep the finFET fab costs down is by using plasma-doping implant chambers. Based on presentations at previous IEDM conferences, finFETs seem to be able to use the most of the same materials and processes as for planar transistors, including high-k metal-gates. However, the change in geometry means that changes will be needed to integrate materials for strained-silicon. Processing details should start leaking over the next year.

-Ed Korczynski

By now, you’ve probably heard that Intel has uncloaked “tri-gate” finFET (a.k.a. Multi-Gate FET or MuGFET) architectures as the company’s 22nm transistor technology for high-volume manufacturing (HVM) of digital ICs. This confirms the rumors that have spread for the last half-year, and proves that this pseudo-3D approach will finally live outside of R&D labs. With much of the IC fab world focusing on low-power chips for mobile applications, the fully-depleted channels of finFETs provide reduced power consumption.

To be sure finFETs are a very attractive way to get to fully-depleted channels and so achieve the lowest possible off-current in transistors. At last year’s IEDM, with rumors of this move by Intel rampant, there was much hallway conversation about the relative merits and demerits of wrapping gates around a fin. In general, there are 2nd-order electrostatic issues associated with the 3D structures so that new possible leakage paths must be controlled. An IEDM evening panel discussion sponsored by Applied Materials featured a discussion on finFETs vs. FD-SOI vs. alternate-channel materials for 22nm node processing. Witek Maszara of GlobalFoundries explained that, “Better electrostatics could come from FD or MuGFET devices, while better transport could come from high-mobility channels.”

Intel first showed tri-gate finFETs for SRAMs in 2006, and claims that only 2-3% additional processing costs are needed to go from planar FETs in high-volume. Consequently, the major advantage of finFETs at 22nm is that no new channel materials will have to be integrated, and the extra cost of silicon-on-insulator wafers can be skipped. Intel did not mention the costs associated with re-spinning all of their designs to be able to go from planar to fins (this will be the topic of a future Siliconisms blog post). To be sure, old planar transistor models must be replaced.

Intel’s promotion of this transistor architecture includes extensive mention of Atom chips and mobile applications. The company clearly wants everyone to still think of Intel when we think of mobile computing, despite the stunning failures of Atom chips to compete with ARM-cores in the last few years. The raw transistor performance boost of 22nm finFETs will certainly provide an advantage over 32nm planar FETs, and so Intel’s less-efficient Atom chips may win some sockets from the ARM hordes while the rest of the industry catches up to 22nm.

-Ed Korczynski

Electron-beam Direct Write (EbDW) lithography on commercial wafers may sneak in the industry behind the technology developments for mask writing. At SPIE AL this year, Aki Fujimora (CEO of D2S and head of the E-beam Initiative) talked with SemiMD about solving today’s mask problems using tricks that will be needed before EbDW can be used in HVM. D2S’ Model-Based Mask-Data Preparation (MB-MDP) software was reported by one IBM engineer to cut up to ½ of the time from mask writing. Xilinx is one of the newest partners in the E-beam Initiative, and as a company built to make some of the largest logic chips in the highest volumes, probably didn’t join because of EbDW.

CEA-Leti and its ASELTA Nanographics spin-out recently announced the start of joint work on e-beam proximity effects corrections for both mask writing and EbDW. A new lab will be staffed inside the multi-partner IMAGINE program, which is designed to develop maskless lithography for IC manufacturing using the Mapper tool. Mentor Graphics just joined IMAGINE, and will develop multiple e-beam lithography data processing flows in the program. “Multi-beam systems for maskless lithography are contenders for next-generation patterning. The IMAGINE program is offering a unique infrastructure to enable this technology and we want to be an early partner in this research,” said Joe Sawicki, vice president and general manager of Mentor’s Design to Silicon Division.

In his SPIE AL keynote, TSMC senior vice president of Research and Development Shang-yi Chiang explained the economic constraints when working on new lithography technologies. For a commercial foundry, the price a customer is willing to pay for a next generation wafer is limited by the price of the current generation. In TSMC’s internal budget for this overage, a full half is due to lithography. “Within transistor and interconnect we do not see any roadblocks,” said Chiang. “So lithography cost is the single greatest factor which may limit our ability to extend Moore’s Law into the next decade.” EbDW could be the only litho used for designs needing only hundreds of wafers, and could cut grid lines in HVM. A Mapper “pre-alpha” tool shipped into TSMC’s Fab12 in July 2009, and was exposing wafers by the end of the year using a 25nm spot size and raster scan writing into 45nm thick resist on BARC.

David Lam (yes, founder of Lam), currently executive evangelist for Silicon Valley start-up Multibeam, provided an excellent overview of the fundamental requirements and constraints of EbDW at SPIE this year. Referring to the term ‘complementary lithography,’ used last year by Yan Borodowsky (Intel’s expert, present in the audience) to describe 193i to form grids complemented by some other lithographic technology to perform sparse cuts, this year Lam tried out the term ‘Complementary E-Beam Lithography’ (CEBL) to mean EBL used in complement to 193i for low-density critical layers. “In my opinion this is the only way that e-beam litho can get into high-volume,” cautioned Lam.

-Ed Korczynski

The lithographers return each February (28^th through March 3^rd this year) to San José (California) for the SPIE conference, in part to see the exhibition of the best new tools and the brightest new sources for patterning nano-scale devices. With multiple technical sessions in parallel, poster/snack sessions, workshops, and evening roundtables it’s a feast for anyone working near fabs, not just lithographers: depositions and etches are key to double-patterning (DP), metrology limits are explored, and designs’ EDA PDK DFM extensions gate yield. From the advance program available online, we can extract some obvious trends, and also spotlight some sessions and presentations as “must sees.”

With the source wavelength stuck in water at 193nm, and all post-optical “next-generation lithography” (NGL) technologies still stuck in R&D, the only way today to form 32nm and smaller structures is to use clever extensions to optical litho like DP and source-mask-optimization (SMO). Such extensions require integration of design and manufacturing technologies to an ever greater extent. DFM is only possible with accurate fab data, so as we push to make ever smaller devices we find the need for ever more capable measuring tools.

EUV has missed the boat for 22/20nm node production, since that process is now in pilot. Thus, the next possible insertion point is the 16/14nm node, which alert readers will notice is almost the same size as the 13.5 nm wavelength of EUV. Since an expensive technology must be useful for more than a few years, whatever patterning technology is developed for 16nm must be extendible to 11nm at least. Consequently, EUV litho will need to be able to be able to pattern below wavelength, which will require greater expense in design (OPC and SRAF), and in manufacturing (more complex and thus more expensive tooling needed). Wikipedia sums up the EUV challenges well.

Big picture trend info will be provided in plenary presentations by Luc Van den hove (President and CEO, IMEC) and Shang-Yi Chiang (Senior Vice President, R&D, TSMC) that start the conference off Monday morning. At the risk of offending by omission, the following are some of the best invited papers at SPIE AL this year:

• Alain Diebold (U.Albany) on “Semiconductor metrology from new transistor and interconnect materials to future nanostructures” [7971-01] MON AM,
• Patrick Naulleau (LBNL) on “Critical challenges for EUV resist materials” [7972-02] MON AM,
• Roel Gronheid (IMEC) on “EUV secondary electron blur at the 22-nm half-pitch node” [7969-03] MON PM,
• Kiyoshi Takamasu (U.Tokyo) on “Subnanometer line width and line profile measurement for CD-SEM calibration by using STEM” [7971-07] MON PM,
• Aki Fujimura (D2S) on “A comparison of maskless technologies” [7970-02] TUE AM,
• Cyrus Tabery (GlobalFoundries) on “Design architecture, metrology, and integration: OPC at the age of discovery” [7973-02] TUE AM,
• Robert Socha (ASML) on “Freeform and SMO” [7973-04] TUE AM,
• Chris Bencher (Applied Materials) on “Mandrel-based patterning: density multiplication techniques for 15-nm nodes” [7973-19] WED AM,
• Mark Bohr (Intel) on “Moore’s Law in the innovation era” [7974-01] WED PM,
• Lars Leibmann (IBM) on “Decomposition-aware DRC to enable double-patterning compliant standard cell libraries” [7974-19] THU PM.

–Ed Korczynski

Ever since Intel pulled Gordon Moore out of retirement to declare that high-k metal-gate (HKMG) transistors were the biggest change to hit the IC industry since the the MOSFET, there has been a battle between Intel and IBM as to which way to go. Intel started at the 4Xnm node with gate-last processing, in which the transistor gate is made after high-temperature anneals, and will continue to use gate-last at 3Xnm and 2Xnm nodes. IBM et al. kept SiON gates at 4Xnm, decided to go with gate-first HKMG at 3Xnm, but has now admitted to rumors that 2Xnm will require a reversal of direction to gate-last.

At the Common Platform (CP) Technology Day in Santa Clara, California last month, representatives of foundry-partners BM, Samsung, and GlobalFoundries discussed the rational for switching between gate-first at 3Xnm and gate-last at 2Xnm. In general, gate-last flows add in two new CMP process steps, while gate-first flows add complexity to the existing process steps. However, gate-last requires relatively greater restrictions on the design rules and re-design of circuitry, such that the areas of chips may increase by 10-20% compared to gate-first. Thus gate-first at 3Xnm can promise a greater number of chips/wafer.

Gate-first at 3Xnm allows for design cost savings when shrinking 4Xnm SiON chips, since poly-jogs and other 2D shapes may still be used. In contrast, 3Xnm gate-last mandates use of extremely restrictive design rules (RDR) such that only 1D line segments may be used in any one layer. RDRs impose additional design costs and final chip area penalties, though generally providing improved fab yield. Since most Intel chips are designed internally, the company can tightly integrate design and manufacturing teams and so can more easily work with RDR compared to others.

Why now plan to use gate-last at 2Xnm? The lithographic process window is stuck with immersion-193nm illumination, such that 2D shapes cannot be formed at 2Xnm. “In density, for 32/28nm gate-first was the best. Different things happen at 20nm, and we had to do local interconnects, so the RDRs limited density,” explained Gary Patton, IBM vice president of semiconductor R&D.

Meanwhile, TSMC will continue to use gate-last at both nodes, potentially saving design costs for shrinks between nodes. Rival foundry UMC, with a hybrid “first+last” flow announced for 3Xnm, will presumably follow with gate-last for 2Xnm. –Ed Korczynski