Part of the  

Solid State Technology


About  |  Contact

IFTLE 393 Samsung Adv Pkging at ECTC: Emphasis on Warpage Control

By Dr. Phil Garrou, Contributing Editor

At the 2018 ECTC, Samsung presented several papers on their advanced packaging activities.

Samsung teamed with SUNY Binghamton to discuss “design Guidelines of 2.5D Package with Emphasis on Warpage Control and Thermal Management.” A 2.5D Package is composed of many material sets and in general its size is larger than conventional single chip packages. The CTE of substrate is a well-known factor to control warpage in a single die packages. However, the existence of another layer (interposer) makes the problem more complicated. Optimization of the material sets, which include lid, EMC, chip, Interposer and geometric factors, are essential.

From their modeling studies it is clear that substrate CTE is more influential than other criteria.

They developed the following guideline for warpage control and thermal management:

Area ratio of lid attach, lid thickness, EMC CTE and substrate CTE are major factors influencing for warpage. For thermal management, EMC coverage on top of the chip, (cooling) fan speed, and conductivity of TIM are the major factors that affect thermal resistance.

In their presentation on “Low Cost Si-less RDL Interposer Pkg for High Performance Computing Applications” In this presentation a concept for a Si-less redistribution layer is descried for server/HPC applications and warpage behavior, electrical performance and reliability of the RDL interposer package were evaluated.

Si-interposer have attracted attention for high end sever products due to  high electrical performance at low power consumption. The key barrier of Si-interposer adoption, utilizing TSV, is high manufacturing cost for large interposer sizes. They suggest a Si-less redistribution layer (RDL) interposer platform for high performance applications as a low cost package solution.

The table below compares 2.5D Si interposer technology to wafer level and panel level RDL interposers.

The fabrication process flow of RDL interposer package is classified into six main steps as summarized in the fig below.  RDL formation, multi-chip bonding on RDL, encapsulation, chip exposure, solder ball attachment, and interposer assembly on PCB. The most challenging aspect of the assembly is reportedly the warpage control of interposer packages, due to the large size and multichips.

Samsung clams that the RDL interposer package has the advantage of lower manufacturing cost over Si-interposer by replacing TSV with RDL. Their results showed that RDL interposer warpage is more controllable than Si-interposer at room and high temperature by the optimization of design, process condition and material selection. Their test structure, a RDL interposer package whose size is larger than 3000mm2 included four HBMs and one ASIC chip, was successfully fabricated and they determined that the electrical loss of RDL interposer was lower than Si interposer case. Mechanical simulation showed RDL interposer reduced joint stress by 34% compared to Si interposer. They predict that RDL interposer tech will become one of the most promising solutions for low cost and large size packages in the near future if “….fine patterning technology is developed below L/S 2/2um.

For all the latest in advanced packaging, stay linked to IFTLE…

Leave a Reply

Extension Media websites place cookies on your device to give you the best user experience. By using our websites, you agree to placement of these cookies and to our Privacy Policy. Please click here to accept.