Part of the  

Solid State Technology

  Network

About  |  Contact

Archive for June, 2018

IFTLE 387 Broadcom Looks to Advanced Packaging; Rumors from ECTC San Diego

Tuesday, June 19th, 2018

By Dr. Phil Garrou, Contributing Editor

Boon Chye Ooi , Sr VP of Operations for Broadcom spoke at the IEEE ECTC luncheon addressing “Packaging advancements to enable artificial intelligence (AI), autonomous cars and wearables in the near future: cost and implications to supply chains.”

Broadcom’s Sam Karikalan, ECTC General Chair introduces Boon Chye Ooi , Sr VP of Operations for Broadcom

Ooi leads the global operations organization which is responsible for worldwide manufacturing including foundry and package engineering, outsourcing, procurement and logistics, planning and quality programs. Ooi indicated that he saw packaging as having played a vital role in enabling semiconductors to penetrate new application frontiers such as artificial intelligence (AI), autonomous cars and wearables, but for their ubiquitous deployment, the packaging community must make these technologies cost competitive and multi sourced.

He had 3 questions for the supply chain:

  1. Is the OSAT/Foundry willing to invest fab like yield tools?
  2. Will there be sufficient capacity and reliability of supply?
  3. How will cost excursions and miss-processing be handled by the infrastructure?

His call to action for the supply chain of 2022 included the following points:

  • Upgrade assembly yield management to Fab level
  • Develop u-bump probe and test technologies for improved yield
  • Develop substrates for low loss mm wave channels on large packages
  • Develop low cost thermal solutions to reduce system cost
  • Develop multiple suppliers for silicon content, packaging raw material, substrate and assembly

Specific technical challenges included the following:

  Desired Goal Issues
Data rate 112 Gbps · channel insertion loss and return loss

· crosstalk

· power integrity

Package Body size > 90 x 90mm · package warpage

· board level reliability

· socket cost and performance penalty

2.5D Integration More and larger dies · interposer reticle size

· assembly challenges

· more memory bandwidth

u-bump pitch < 30um · assembly challenges

· routing challenges

 

Power dissipation >500W · thermal interface materials

· heatsink solutions

 

Rumors from San Diego

With 1750 attendees present there were sure to be numerous rumors making the rounds at ECTC. In time some will clearly turn out to be true and some will not, but all of them are certainly interesting enough to consider.

One rumor I can confirm is that Rao Tummala, unquestioned “Father of Microelectronics Packaging”  will be retiring imminently. Tummala, now in his mid 70’s, has informed Ga Tech and his PRC that a successor should be located. He will be helping his replacement for a few years to ensure a smooth transition but he is looking forward to relaxing, spending more family time and playing more golf. It certainly will be interesting to see who Ga Tech finds to fill his shoes.

As I have detailed several times in IFTLE, BT (before Tummala) packaging was an after thought carried out by failed front end engineers. In 1989 Tummala, while still at IBM, joined Gene Rymaszewski editing the first Microelectronic Packaging Handbook categorizing this technology for the first time. In 1993 Tummala left IBM to set up an NSF PRC (packaging research enter) at Georgia Tech to explore and develop packaging concepts and, just as importantly, educate highly-interdisciplinary students in this concept. This NSF funding was supplemented by more than 50 U.S. companies and the State of Georgia. 20 new faculty were recruited with expertise in every electronics area. The 1st of a kind cleanroom pilot line for package, assembly and reliability was built at a cost of $47M. In the intervening years more than 400 PhD, 470 MS and 340 BS engineers all specializing in packaging have graduated from this program and populated the electronics companies around the world. In 1997 the Packaging handbook was rewritten in 3 volumes and more than 2000 pages. The chapter author list is a who’s who in the field of packaging. I am proud to have been part of that endeavor. Below is a photo we took in Slovenia together 21 years ago in 1997.

In 2001, Rao produced what I consider the first undergrad / grad packaging text “Fundamentals of Microsystem Packaging,” which has been used to teach electronics packaging in many of our universities. He and I co-wrote the chapter on wafer level packaging, a new concept at that time. My point in reciting all this is to simply backup my statement that these will be very large shoes to fill. It will be interesting to see who will fill them.

For all the latest in Advanced Packaging, stay linked to IFTLE…

 

IFTLE 386 IEEE EPS Awards at 2018 ECTC

Wednesday, June 13th, 2018

By Dr. Phil Garrou, Contributing Editor

Memorial Day in the US means the start of the IEEE ECTC meeting, which is run by the IEEE EPS society (Electronic Packaging Society). This years 68th meeting was in San Diego and broke all records with an attendance of > 1750. There were 369 presentations in 36 oral sessions (6 in parallel) with authors from 28 countries.

The exhibition has been at capacity for several years with 106 exhibitors and reportedly 40+ on a wait list. IFTLE concludes that eventually this meeting must move to convention centers because it is becoming too large for hotel spaces available.

In this first blog on 2018 ECTC we will look at the EPS 2018 award winners.

The IEEE EPS Field Award

As we have discussed in the past the major packaging award in the world is the EPS “Field Award” meaning the top award in the “field.” This year’s winner is Bill Chen from ASE. The photo below shows IEEE President Jose Moura giving the award to Bill.

Dr. Bill Chen accepts EPS Field Award

Bill received his engineering education at University of London (B.Sc), Brown University (M.Sc) and Cornell University (PhD).  He joined IBM Corporation at Endicott New York in 1963. At  IBM  he  worked  in  a  broad  range  of  IBM microelectronic packaging products. He received IBM Division President Award for his leadership and innovation in Predictive Modelling on IBM products.    He was elected to the IBM Academy of Technology for his contributions to IBM Products and Packaging Technologies. He retired from IBM in 1997.  He joined the Institute of Materials Research and Engineering (IMRE) in Singapore, as Director of the Institute till 2001 when he joined ASE Group, where he holds the position of ASE Fellow and Senior Technical Advisor with responsibilities for guidance to technology strategic directions for ASE Group.

He is Senior Past President of the IEEE/CPMT Society. He is the Co-Chair of the ITRS Assembly and Packaging Roadmap Technical Working Group. He is a Fellow of IEEE and Fellow of ASME.  He has served as an Associate Editor  of ASME Journal of Electronic Packaging, and IEEE/CPMT Transactions.

EPS Electronics Manufacturing Technology Award

The 2018 IEEE EPS Electronics Manufacturing Technology Award was given to Douglas Yu of TSMC for “contributions to the development and high volume manufacturing of interposers and wafer level fan out packaging”. Dr. Yu received his B.S. degree in Physics and M.S. degree in Materials Science and Engineering both from National Tsing Hua University, and his Ph.D. in Materials Engineering from Georgia Institute of Technology. Dr. Yu was appointed TSMC’s Vice President in November 2016. Dr. Yu joined TSMC in 1994. He was previously Senior Director of the Integrated Interconnect & Packaging Division, where he led the development of interconnect technology for integrated circuits. Below we see Dr. Yu (L) accepting his award from EPS President Avi Bar Cohen.

Doug Yu receives Electronic Manuf Award

The IEEE EPS Outstanding Sustained Technical Achievement Award went to Professor Pradeep Lall of Auburn for “outstanding sustained contributions to the design reliability and prognostics for harsh environment electronic systems”.

The IEEE EPS Exception Technical Achievement Award went to three practitioners in the 2.5/3D technical space: Prof Mohannad Bakir of Georgia Tech; Prof Kuan-Neng Chen of National Chiao Tung Univ in Taiwan and Dr Katsuyuki Sukama of IBM.

All the awards were for “contributions to 2.5 and 3D IC heterogeneous integration, with focus on interconnect technologies.”

The IEEE EPS David Feldman Outstanding Contribution award went to EPS past president Jean Trewhella for “20 years of leadership consistently driving change collaboration and engagement in EPS and ECTC, including driving our society name change, sponsoring the heterogenous Integration roadmap and establishing the ECTC student reception.”

Newly elected Fellows included:

Kuan-Neng Chen – National Chiao Tung Univ , Taiwan
Klaus-Dieter Lang – Fraunhoffer IZM, Germany
Jinmin Qu – Northwestern Univ
Guo-Quan Lu – VPI
Saibal Mukhopadhyay – Georgia Tech
Stefan Grivet-Talocia – Politecnico de Turino, Italy

…and while we are talking awards.

Corning Presents First Annual ‘Corning Leadership in Glass Award’ at ECTC 2018

At the ECTC, Corning presented the first annual “Corning Leadership in Glass Award” to Proff Rao Tummala and his group at Ga Tech. The award recognized the technical paper “Design and Demonstration of Highly Miniaturized, Low Cost Panel-Level Glass Package for MEMS Sensors,” submitted by Georgia Tech at ECTC 2017 that best demonstrated the viability of glass for semiconductor packaging applications.

“We’re pleased to accept this very special award from Corning,” said Tummala. “We have long believed that the properties and fabrication of ultra-thin glass make it the best next generation material of choice for semiconductor and system package integration manufacturing processes after metal-based packaging since 1970s, ceramics since 1980s, organic laminates since 1990s and silicon since 2010. We’re proud that the research we’ve done in glass panel packaging in both chip-first and chip-last architectures, is gaining more and more acceptance.” Because of this special and unique nature of glass packaging, we converted our whole Center to glass packaging for high-bandwidth computing, 5G communications, power, mems and sensors and others.”

Dr. Venky Sundaram, Chintan Buch (student), and Prof. Rao Tummala (left to right) accept the inaugural ‘Corning Leadership in Glass Award’ at ECTC 2018.

For all the latest on advanced packaging, stay linked to IFTLE…

IFTLE 385 Samsung’s Semiconductor Focused Activities

Friday, June 8th, 2018

By Dr. Phil Garrou, Contributing Editor

Let’s take a look at Samsung’s System LSI activities per their recent Investor program. ICs and applications that were highlighted are shown below.

Chronological advances in the Exnos microprocessor which are now being manufactured at 10nm are shown below.

Samsung has maintained a position as supplier of mobile processors, image sensors and display driver ICs. Looking into the future Samsung sees the main application drivers as:

Samsung System LSI is a provider of integrated total solution for mobile. They feel that innovations in semiconductor technologies will be the key driver in various new applications that adopts AI/Deep Learning, 5G networking, and smart mobility. Samsung LSI is now on the path to be a key player for 5G and autonomous mobility, and is investing for future device intelligence.

This will require a lot of advanced packaging!

For all the latest in advanced packaging, stay linked to IFTLE…


Extension Media websites place cookies on your device to give you the best user experience. By using our websites, you agree to placement of these cookies and to our Privacy Policy. Please click here to accept.