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Archive for March, 2018

IFTLE 376 ASE / TDK launch ASE Embedded; The AI Ecosystem Develops

Tuesday, March 27th, 2018

By Dr. Phil Garrou, Contributing Editor

ASE, TDK Embedded Chip Joint Venture begins

Taiwan’s ASE has initiated a joint venture with Japan’s TDK Corp to produce embedded packaging solutions in Kaohsiung Taiwan. ASE has 51% ownership in the venture which currently employs 150 people.

With initial capital of $51MM , ASE Embedded Electronics Inc has started operations manufacturing embedded substrates using TDK’s (SESUB) technology (see IFTLE 238 “ASE & the Apple watch, ASE / TDK JV…” and IFTLE 347: “ASE Embedded Packaging Solutions” )

ASE 1-4

AI vs IoT

AI and IoT both buzz words that are predicted to drive the electronics industry over the next decade. ITLE is bullish on AI, not so much on IoT. As I have explained before my opinion is formed from a packaging perspective and while I think AI will need all the latest high end packaging solutions, I still perceive that most IoT will require the absolute lowest cost, stripped down packaging available. AI platforms are an intimate combination of hardware and software but certainly will be requiring the latest that we have to offer in high end packaging solutions.

AI processing will go into home control devices, autos, surveillance systems, airplanes, wearables and things we have yet to think of. AI processing is unique in that traditional customers Amazon, Google and Apple, have begun to design their own AI chips, in hopes of differentiating their products from those of rivals. This has major ramifications for companies like Intel and Nvidia, which will now be competing with their customers.

While I certainly am not an AI expert, we all must quickly up our knowledge in this area which I see leading advanced packaging into the next decade. A list of current participants has recently been compiled (shown in the table below) (link)

table

Recently on “Graphics Speaks” Kathleen Maher has looked at how some of these cloud companies, IP companies, and the traditional semiconductor companies all have conflicting ambitions in the AI market place . I recommend reading the full article.[link]

While cloud companies like Google appear to be favoring custom chips to augment CPUs and GPUs, Semiconductor and IP companies are designing chips to enable efficient hardware and neural net systems and Intel is proposing an open platform ecosystem based on Xeon, FPGAs, and specialized processors like Nervana and Saffron.

Google

Google’s Tensor Processing Unit (TPU), was introduced last year. Their initial beta customer Lyft, is using AI to recognize surroundings, locations, street signs etc. The cloud-based TPU features 180 teraflops of floating-point performance through four ASICS with 64 GB of high bandwidth memory. These modules can be used alone or connected together via a dedicated network to form multi-petaflop ML supercomputers that they call TPU pods.

Apple

The best known mobile AI processor is included in the Apple iPhone X. Apple’s A11 is a 64-bit ARM 6 core CPU with two high performance 2.39 GHz cores called Monsoon, and four energy efficient cores, call Mistral. The A11’s performance controller gives the chip access to all six cores simultaneously. The A11 has three-core GPU by Apple, the M11 motion coprocessor, an image processor supporting computational photography, and the new Neural Engine that comes into play for Face ID and other machine learning tasks.

Amazon

Amazon is reportedly developing a chip designed for artificial intelligence to work with the Echo and other hardware powered by Amazon’s Alexa virtual assistant (link). The chip should allow Alexa-powered devices to respond more quickly to commands, by allowing more data processing to be handled on the device vs the cloud.

Nvidia

Nvidia has announced its new Volta GPU with 640 tensor cores, which delivers over 100 Teraflops. It has been adopted by leading cloud suppliers including Amazon, Microsoft, Google, Oracle , and others. On the OEM side, Dell EMC, HP, Huawei, IBM and Lenovo have all announced Volta-based offerings for their customers.

Microsoft and Intel’s “Brainwave”

Microsoft has teamed with Intel and is offering their Stratix 10 FPGAS for AI processing on Microsoft Azure (see below) codename “Brainwave” (link) . Intel is proposing FPGAs  + processors for AI work. Intel is reportedly focusing on the Stratix X FPGA as a AI companion to Intel’s Xeon processors.

Microsoft

 

Intel’s 14 nm Stratix 10 FPGAs accelerate Microsoft’s Azure deep learning platform using FPGAs with “soft” Deep Neural Network (DNN) units synthesized onto the FPGAs instead of hardwired Processing Units (DPUs). Brainwave is designed for live data streams including video, sensor feeds, and search queries.

Intel

Intel is making a major play in AI. Intel has multiple processor options for AI, including Xeon, FPGAs, Nervana, Movidius, and Saffron (link).

Saffron Technology was acquired by Intel in 2015. It develops “..cognitive computing systems that use incremental learning to understand and unify by entity (person, place or thing) the connections between an entity and other “things” in data, along with the context of their connections and their raw frequency counts…. Saffron learns from all sources of data including structured and unstructured data to support knowledge-based decision making.” It is being used extensively in the financial services industry.

In 2016, Inte­­­l announced acquired Nervana, a startup developing AI software and hardware for machine learning. In 2017, Intel revealed the Nervana Neural Network Processor (NNP) designed expressly for AI and deep learning.

Intel acquired Movidius in 2016 to get VPU (visual processor unit) technology for machine learning and AI. Intel’s Movidius devices include dedicated imaging, computer vision processing, and an integrated neural compute engine. Applications for VPUs include automobile license readers at bridges and toll roads, airport security screening, drone surveillance and the many applications of facial recognition.

ARM – Trillium Platform

The Arm Trillium Platform includes Machine Learning (ML) and Object Detection (OD) processors with Arm software, and the existing Arm compute library and CMSIS-NN Neural Network kernels.

 

It will be interesting to see hope the packaging community develops solutions that will be compatible with these advanced high speed HPC applications.

For all the latest on advanced packaging, stay linked to IFTLE…

IFTLE 375 EVG / IBM Laser Debonding; Samsung Increases Focus on CMOS Image Sensor Mkt

Tuesday, March 20th, 2018

By Dr. Phil Garrou, Contributing Editor

EVG Licenses IBM Laser deBonding Tech

IBM’s Hybrid Laser Release Process has been licensed by EV Group for inclusion in their low-temperature laser debonding equipment (link).

The IBM technology will reportedly help EVG address the industry’s requirements for temporary bonding and debonding, including high throughput, low wafer stress for high yield, and low cost of ownership of the laser equipment, processing and consumables. The EVG offering will encompasses techniques to help protect chips from heat and laser damage, as well as chemical clean technologies for device and carrier wafers.

The IBM technology was first described at the 2010 IEEE ECTC Conf (link)

Post debond cleaning is a topic that is rarely discussed but very significant from a manufacturing standpoint. Following debonding, residual polymer materials are left on the substrate. The residue level is dependent on the ablation condition. Laser fluence and total accumulated number of laser pulses need to be optimized for a given polymer adhesive. After debonding, any residue or remaining polymer adhesive needs to be cleaned prior further processing. The cleaning may be accomplished by several approaches including dry etching or chemical wet etching.

EVG 2

 

Designed for integration in the company’s benchmark EVG-850DB automated debonding system, EVG’s laser debonding modules incorporate a solid-state laser and optics designed to enable force-free debonding. Featuring both low-temperature debonding and high-temperature-processing stability, EVG’s laser debonding solution is available for a variety of applications including FO-WLP (below), memory stacking, die-partitioning, heterogeneous integration etc.

EVG debonding

Samsung to Challenge Sony on CMOS Image Sensors

Fresh from their overtaking of Intel as the worlds #1 IC Chip producer, ETNews (Korea) reports that Samsung has reportedly now set its sights on Sony and CMOS Image sensors. (link)

Samsung Electronics is reportedly planning to increase its production capacity of image sensors and it has set a goal to become #1 in the image sensor market.

Since 2017, Samsung has reportedly been working to convert its line 11 in Hwasung that was used to produce DRAMs into a line (S4 line) that would be used to produce CMOS image sensors (CIS). Conversion to the S4 line is expected to be completed by end of this year. According to ETNews Korea , when this process is done, Samsung Electronics is going to immediately start the conversion process of its 300mm line 13 in Hwasung, that is used to produce DRAMs, into another line that will be used to produce image sensors. Line 13 line can produce about 100,000 units of DRAMs per month, but because image sensors ae a more complex deposition process, it is expected that production capacity for CIS will be reduced by about 50% after conversion. They further report that Samsung Electronics will have a total production capacity of 120,000 units / mo of CIS after these conversion processes are over.

SONY and Samsung are both commercializing 3D stacked image sensors (sensor + logic + DRAM) that can process 960 frames per second (slo-mo). Samsung Electronics has launched the new ISOCELL Fast 2L3 image sensor for super slow-motion recording (link).

The Samsung ISOCELL Fast 2L3 is a high speed 3 layer 3D stacked CMOS image sensor designed with a 2 Gb LPDDR4 DRAM attached below the analog logic layer. With the integration, the image sensor can temporarily store a larger number of frames taken in high speed quickly onto the sensor’s DRAM layer before sending frames out to the mobile processor and then to the device’s DRAM. This allows the sensor to capture a full-frame snapshot at 1/120 of a second and also to record super-slow motion video at up to 960 frames per second ( 32 times the typical filming speed of 30 fps).

samsung

The design is similar to that of Sony who was the first to report integration of DRAM into the 3D CIS stack (see IFTLE 272 “2015 3D ASIP Part 1: Pioneer Awards; Sony 3D stacked CIS; Latest on SPIL Acquisition”)

ETNews reports that the number of customers purchasing Samsung image sensors is currently over 10 as Samsung Electronics is increasing points interactions with major mobile devices and automotive customers.

For all the latest on advanced packaging, stay linked to IFTLE…

 

IFTLE 374 IMAPS Device Pkging Conf part 1: 3DIncites Award Winners

Monday, March 12th, 2018

By Dr. Phil Garrou, Contributing Editor

The 14th Int Conf on Device Pkging was held at its normal site, Ft. McDowell, AZ, last week. I normally show a picture of the general chair of the meeting and I will this time also (below), but I thought it was about time we gave due credit to the IMAPS staff that makes the meeting possible.   Below we see (L to R) Dir of Program Dev, Brian Schieman; Membership Admin, Shelby Moirano and Exec Dir Michael O’Donoghue. Events Mgr Brianne Lamm was back in NC holding down the fort, so to speak.

IMAPS CREW

 

On Tuesday night, we were all entertained by a local Indian tribe that showed us their various ceremonial dances. Below Chairman Ramm poses with the tribes dancers.

Ramm & the Indians

 

The most entertaining event of the conference was certainly the 3DInsights awards gala on Wednesday night which included, in addition to the awards ceremony, a barbecue dinner, an awards ceremony quiz and a dress up photo booth.

There were 40 nominees from 26 companies and four research institutes competing for awards in 9 categories. An amazing 40,619 votes were cast online. Winners were:

Device Manufacturer of the Year: Amkor Technology for its acquisition of NANIUM.

Device of the Year: (tie) M-Series ™ Deca Technologies, and OmniVision Technologies. Deca was nominated for their adaptive processing technology combined with planar front side molding. OmniVision was nominated for their Nyxel technology which allows their image sensor to see better and farther under low- and no-light conditions than previous generations.

EDA Supplier of the Year: Mentor, A Siemens Business was nominated in recognition of the efforts of Juan Rey, VP of Engineering, at a number of 3D-IC focused conferences in 2017.

Engineer of the Year: Gill Fountain, Xperi (Ziptronix) was nominated for expanding the chemical mechanical polishing process window for Cu damascene image sensor processing.

Equipment Supplier of the Year: FRT GmbH was nominated in recognition of its third gen surface metrology tools that combine multi-sensor technology and hybrid metrology in one measuring system.

Material Supplier of the Year: Semblant for their MobileShield technology, a nano-coating that protects mobile phones from water damage and corrosion.

Process of the Year: F.A.S.T., KOBUS  was nominated for combining the CVD and ALD deposition.

Research Institute of the Year: Fraunhoffer IZM  was nominated for launching a consortium to bring research and industry together on all questions of implementing panel level packaging (PLP)

The dress up photo booth was certainly lots of fun. Below we see General Chair Peter Ramm, 3DIncites Francoise von Trapp and a group shot of the nights award winners.

awards

Proceeds from the event went to two charities: the IMAPS Microelectronics Foundation, which exists to support student activities related to the study of microelectronic packaging, interconnect and assembly; and Phoenix Children’s Hospital pediatric oncology programs which exists to save children with cancer.

Next week we will start to look at some of the key presentations.

For all the latest in Advanced Packaging, stay linked to IFTLE…