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IFTLE 369 Samsung HBM2; Ultra Fine Pitch Interconnect; Thin Die Pick and Place

By Dr. Phil Garrou, Contributing Editor

First introduced in June 2016, the Samsung HBM2 consists of eight 8Gb HBM2 dies and a buffer die at the bottom of the stack, vertically interconnected by TSVs and µbumps. With each die containing over 5,000 TSVs, a single Samsung 8GB HBM2 package has over 40,000 TSVs. Including spares TSVs ensures high performance, by enabling data paths to be switched to different TSVs when a delay in data transmission occurs. The HBM2 is also designed to prevent overheating beyond certain temperature to guarantee high reliability. The HBM2 reports a 256GB/s data transmission bandwidth, offering more than an 8X increase over a 32GB/s GDDR5 DRAM chip. With capacity double that of 4GB HBM2, the 8GB solution contributes greatly to improving system performance and energy efficiency, offering ideal upgrades to data-intensive, high-end computing (HPC) applications that deal with machine learning and graphics processing .

Last week Samsung announced that it has started mass production of its 2nd-generation 8-gigabyte (GB) High Bandwidth Memory-2 (HBM2) with the fastest data transmission speed on the market today.[link] Dubbed “Aquabolt”, it is claimed to be the industry’s first HBM2 to deliver a 2.4 gigabits-per-second (Gbps) data transfer speed per pin, at 1.2V for the supercomputing and the graphics card market.

This performance is reportedly 50% greater than the 1st-generation 8GB HBM2 package with its 1.6Gbps pin speed at 1.2V and 2.0Gbps at 1.35V.

A single Samsung 8GB HBM2 package will offer a 307 GBps data bandwidth, achieving 9.6 times faster data transmission than an 8 gigabit (Gb) GDDR5 chip, which provides a 32GBps data bandwidth. Using four of the new HBM2 packages in a system will enable a 1.2 terabytes-per-second (TBps) bandwidth.

In addition, Samsung increased the number of thermal bumps between the HBM2 dies, enabling better thermal control in each package. The new HBM2 also includes an additional protective layer at the bottom, which increases the package’s overall physical strength.

Samsung HBM2

 

Continuing our look at the presentations at the 14 3D ASIP Conference.

Micross – Ultra Fine Pitch Interconnect

Matt Lueck of Micross gave a presentation on their Ultra fine pith interconnect technologies that are being used in their Northrup Grumman (NGC) DARPA CHIPS program discussed in IFTLE 367 [link].

Fine pitch (< 80 um), Cu pillar thermo-compression bonding (TCB) has been widely adopted for advanced packaging of stacked memory and many other applications. Major foundries and assembly houses are offering Cu pillar down to 30 – 50µm pitch with 20 – 30µm pitch in development. Availability of fine pitch Cu pillar bumping from foundries and OSATs are limited to high volume customers and off-shore processing.

Micross has been developing fine pitch technologies over the years under their previous ownership ( Microelectronic Consortium of NC (MCNC) and Research Triangle Institute (RTI). They re positioning themselves as a source for prototype and small volume production of such ultra high pitch interconnect.

They have used 10µm pitch Cu/Sn – Cu bonding in multiple programs since 2007 such as large area array detector applications. They report that such interconnect have shown proven reliability, even for heterogeneous integration with CTE mismatch issues.

  • For next generation area array imaging applications, sub-10 µm pitch electrical interconnects are desired between detector chip and ROIC
  • A process for the fabrication and bonding of 5 µm pitch Cu-Cu interconnects was demonstrated
  • I-V curves indicate ohmic behavior of interconnect chains
  • Leakage current measurements indicate > 100 GΩ isolation between adjacent channels of interconnects
  • Demonstrated high yield on 1280 x 1024 array sample

Micross 1

Working with NGC they are developing 4 – 10µm pitch gold-gold bonding technology. The evaporated gold bumps show RMS roughness of 3.7-3.9nm.

micross 2

BESI- Thin Die Pick and Place

Stefan Behler of Besi discussed “How to peel Ultra this dies from Wafer tape”

Behler describes 4 key properties as shown below:

BESI 1

(1) Wafer foil peel force depends on the foil type and the peel speed as shown in table below.

besi 2

(2) edge peel force depends on the dicing method

(3) Bending stress depends on the Ejector type with thinned die resulting in more bending stress.

besi 3

 

(4) die strength appears (measured by 3 point bending test) is almost independent of thickness but is dependent on :

  • surface (active structure)
  • backside (grinding, polishing…)
  • edges (dicing)

For all the latest in Advanced Packaging, stay linked to IFTLE…

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