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IFTLE 365 Altera FPGA with HMB2 and EMIB; IWLPC 2017 Part 2

By Dr. Phil Garrou, Contributing Editor

Merry Christmas and Happy New Year to One and All


Intel Altera release Stratix 10 FPGA with HBM2 memory and EMIB connections

Before we continue our coverage of the 2017 IWLPC, I need to make sure everyone has seen the announcement from Intel (Altera) on the availability of the Intel Stratix 10 MX FPGA, their FPGA (field programmable gate array) with integrated HBM2 (High Bandwidth Memory). [link]

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The Intel Stratix 10 MX FPGAs, utilizing Intel’s 14 nm FinFET process, reportedly offer up to 10X the memory bandwidth as compared to standard DDR 2400 DIMM standalone memory solutions. In HPC environments, the ability to compress and decompress data before or after mass data movements is paramount. HBM2-based FPGAs can reportedly compress and accelerate larger data movements compared with stand-alone FPGAs.

The Intel Stratix 10 MX FPGA family provides a maximum memory bandwidth of 512 Gb per second through the integrated HBM2. The Intel Stratix 10 MX FPGA family utilizes Intel’s EMIB technology (Embedded Multi-Die Interconnect Bridge) for high density connections. IFTLE thinks this is the first commercial implementation of EMIB technology in the industry.

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IWLPC part 2


Brubaker and Strothman of KNS discussed the “Application of Infrared Inspection to Thermo-compression bonding and die placement”.

In die placement processes, accurate die placements are required to ensure the formation of functional and reliable electrical interconnections. Verification of accurate die placement can be a challenge for standard flip chip products where there are no patterned features on the backside of die. Cross-sectioning or X-ray inspection can be done, but cross-section inspection requires that samples be epoxy under-filled, ground, polished, and inspected using a microscope. X-ray inspections typically require offline processing with dedicated equipment.

In situ measurement within the die placement equipment itself would be preferable. Typically, die placement machines are equipped with a camera which is utilized for target alignment operating within the visible spectrum. The addition of infrared inspection capability to die placement equipment resolves the limitations presented for in situ visible inspection. Because silicon is transparent to infrared light, an infrared inspection system is able to see through the blank backside of die to detect internal metal patterns. Silicon wafers and die which have been back thinned using a fine grind or polishing process are excellent candidates for infrared inspection. Wafers which were back thinned using coarser mechanical grinding (2000 grit and 1200 grit) yielded lower quality infrared images. The impact of this limitation is believed to be minimal, since most high-end die which require high accuracy placement are evolving to thinner packages which already require fine surface finish to prevent die cracking and wafer warping.

In addition to surface finish, die designs must include features which can be used to generate images with sufficient quality to measure die offsets. In many cases, no special considerations are required in terms of die design. If the absolute best possible placement capability is desired, it is noted that dies which include features optimized for infrared inspection will maximize measurement capability.


Bellman and co-workers from Corning Glass discussed “Temporary Bonding for High Temp Processing of Thin Glass”.

Their “Advanced Lift-off Technology (ALOT)”, is a temporary wafer bonding method for thin glass which reportedly permits subsequent processing over 400C. Fluorocarbon plasmas modify the surface of the glass permitting subsequent controllable van der Waals bonding between a thin glass plates at room temperature. This modification can withstand the vacuum, thermal, wet processing steps of BEOL processing. However, the bond energy between the pair remains low-enough after the thermal processing steps that renders the pair fully detachable.

The ALOT process involves treating a clean hydroxylated glass carrier surface in low-pressure plasma containing CHF3 (or C4F8) and CF4 gases. The CHF3 gas acts as a polymerizing agent and deposits organic fluorocarbon species on the glass carrier while CF4 acts as an etchant and tends to etch away both glass and the organic polymer deposited by CHF3.

In the figure below they plot the bond energy as function of annealing temperature for glass to glass carrier without ALOT treatment (marked as “glass on glass”) and for thin glass bonded to ALOT treated glass carrier corresponding to three initial surface energies (40 mJ/m2, 55 mJ/m2, 72 mJ/m2). The bond energy of untreated glass to glass pair increases exponentially after 200 °C rendering the pair permanently bonded due to covalent bonding. On the other hand, the bond energy of thin glass and ALOT-treated glass carrier pair remains fairly constant at a moderate value up to 400 °C irrespective of the initial surface energy of the glass carrier. This renders the thin glass- glass carrier pair de-bondable after ay post processing which experiences a maximum temperature excursion of ~350-400.

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Barker and co-workers at SPTS discussed “RC Management for Next Gen PVD UBM/RDL Metallization Schemes”.

Organic materials such as PI or PBO dielectric passivation, epoxy mold compound (EMC), or adhesives for bonded wafers with 2.5D and 3D TSV) have the potential to contaminate under bump metal (UBM) or redistribution layers (RDL) producing a potentially undesirable increase in electrical contact resistance (Rc). With the reduction of UBM/RDL via dimensions in line with device shrinks, contamination effects become more critical.

When placed under vacuum and heated, organics will outgas moisture significantly more than traditional ‘front-end’ dielectrics such as SiN and SiO2. When those same organics are sputter-etched during the subsequent UBM/RDL pre-clean step to remove native oxide from exposed metal contacts, they release volatile carbon by-products from their surfaces. Both moisture and carbon by-product contaminants can react with the cleaned exposed metal pad contacts, forming a layer that increases the contact resistance of overall metallization interconnect scheme produced. The problem is particularly acute with advanced node devices with small contact area dimensions where the contaminant has a proportionally larger impact.

New package schemes such as FOWLP can include wafers that feature singulated die embedded in epoxy mold compound (EMC), and have organic dielectrics surrounding the RDL. These materials present challenges, including moisture absorption, excessive outgassing and a limited tolerance to elevated temperatures. Whereas conventional circuits built on silicon can withstand heat up > 400C and can be degassed rapidly without impacting system throughput, the presence of any EMC, organic dielectrics, or bonding adhesives introduces a lower heat tolerance which can be as low as 120C. Temperatures exceeding these lower thresholds can cause decomposition of the organic based materials, in EMC case; it can lead to excessive wafer warping. Degassing wafers at such low temperatures naturally takes a longer amount of time.

Multi-wafer degas (MWD) technology has emerged as a solution to this problem, enabling many wafers to be degassed at 120C in parallel before being individually transferred to subsequent process steps, without breaking vacuum. Each wafer can spend up to 30 minutes inside the MWD, but because they are processed in parallel, a “dry” wafer is outputted for metal deposition every 60 to 90 seconds, at a rate of between 30 to 50 wafers per hour. This approach increases PVD system throughput by 2-3 times.

If a wafer with organics present isn’t degassed sufficiently prior to pre-clean it can produce high levels of outgassing that affect plasma stability during etch, and film quality (Rc) during subsequent sputter deposition. As the surface of the wafer is etched during the pre-clean step, native oxide is removed from the exposed metal contact, but the ion bombardment damages the surface of the organic passivation, releasing volatile carbon species, which, re-contaminates the metal contacts.

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2 Responses to “IFTLE 365 Altera FPGA with HMB2 and EMIB; IWLPC 2017 Part 2”

  1. PWM Says:

    Stratix 10MX with HBM2 was not the first commercial use of EMIB. Other Stratix 10 variants (GX, GTX and GXE etc.) already used EMIB to interface SerDes dies. (See ) Some of those sampled to early customers about a year earlier.

  2. Puja Says:

    The interposer and fan-out WLP market is expected to be valued at USD 13.42 Billion by 2022, growing at a CAGR of 28.09% between 2016 and 2022. The growth of this market is mainly driven by the rising trend of miniaturization of electronics devices; increasing demand for advanced architecture in smartphones, tablets, and gaming devices; and increased usage of advanced wafer level packaging technologies in MEMS and sensors.
    The major players operating in the interposer and fan-out WLP market include Taiwan Semiconductor Manufacturing Company Limited (Taiwan), Samsung Electronics Co., Ltd. (South Korea), Toshiba Corp. (Japan), ASE Group (Taiwan), Amkor Technology (U.S.), Qualcomm Incorporated (U.S.), Texas Instruments (U.S.), United Microelectronics Corp. (Taiwan), STMicroelectronics NV (Switzerland), Broadcom Ltd. (Singapore), Intel Corporation. (U.S.), Jiangsu Changing Electronics Technology Co., Ltd. (China), and Infineon Technologies AG (Germany).
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